Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated
Reexamination Certificate
2001-07-27
2004-08-24
Vigushin, John B. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
C257S704000, C257S783000, C438S118000, C438S126000
Reexamination Certificate
active
06781248
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates generally to methods for packaging an assembly including a semiconductor die and a substrate element, such as an interposer or a carrier substrate and, more specifically, to a method for introducing an encapsulant material over intermediate conductive elements electronically connecting a semiconductor die and a substrate element. Particularly, the method of the present invention includes disposing tape between the semiconductor die and the substrate element, the intermediate conductive elements being located within a slot formed in the tape, and introducing encapsulant material into the slot.
2. Background of the Related Art
The dimensions of many different types of state of the art electronic devices are ever decreasing. To reduce the dimensions of electronic devices, the way in which the microprocessors, memory devices, other semiconductor devices, and other electronic componentry of these devices are packaged and assembled with circuit boards must become more compact.
One approach to reducing the sizes of assemblies of semiconductor devices and circuit boards has been to reduce the profiles of semiconductor devices and other electronic components upon carrier substrates (e.g., circuit boards) by reducing the distances the semiconductor devices or other electronic components protrude from the carrier substrates. Various types of packaging technologies have been developed to facilitate orientation of semiconductor devices upon carrier substrates in this manner.
“Flip-chip” technology, one example of which is termed controlled collapse chip connection (C-4) technology, is an example of a packaging and assembly technology that results in a semiconductor device being oriented substantially parallel to a carrier substrate, such as a circuit board. In flip-chip technology, the bond pads or contact pads of a semiconductor device are arranged in an array over a major surface of the semiconductor device. Flip-chip techniques are applicable to both bare and packaged semiconductor devices. A packaged flip-chip type semiconductor device, which, when an array of discrete conductive elements is located over the major surface, is referred to in the art as a “ball grid array” (BGA) package, typically includes a semiconductor die and a substrate, which is typically termed an “interposer.”
When the interposer of a ball grid array package is positioned adjacent the front surface of the semiconductor die thereof, the bond pads of the semiconductor die on one side of the interposer may be electrically connected to corresponding contact areas on a surface of the opposite side of the interposer by way of intermediate conductive elements, such as bond wires, that extend through one or more holes formed in the interposer. The contact areas communicate through conductive traces with corresponding contact pads bearing discrete conductive elements. In this type of flip-chip semiconductor device assembly, the contact pads are located on the same side of the interposer as the contact pads. This type of flip-chip assembly is positioned adjacent a carrier substrate by orienting the interposer with the contact pad-bearing side thereof facing the carrier substrate.
The contact pads of the interposer are disposed in an array that has a footprint that mirrors an arrangement of corresponding terminals formed on a carrier substrate. Each of the bond (on bare flip-chip semiconductor dice) or contact (on flip-chip packages) pads and its corresponding terminal [as the contacts pads] may be electrically connected to one another by way of a conductive structure in the form of a discrete conductive element, such as a solder ball, that also spaces the interposer some distance away from the carrier substrate. The space between the interposer and the carrier substrate may be left open or filled with a so-called dielectric “underfill” material that provides electrical insulation between the semiconductor device and the carrier substrate and enhances the mechanical connection between the two components.
In addition, the intermediate conductive elements that connect the bond pads of the semiconductor die to their corresponding contact areas on the substrate may be encapsulated by introducing material into the opening or openings of the interposer from above the contact pad-bearing side thereof “Glob-top” type encapsulant materials, such as silicones or epoxies, are typically used for this purpose. Typically, glob-top encapsulant materials have a relatively high viscosity so that the material may be applied to a substantially planar surface without being laterally confined over a particular area of that surface. In comparison with lower viscosity molding materials, such as transfer molding compounds, which are typically used with some structure to laterally confine the molding material over a specific region of an interposer, the height of the resulting glob-top-encapsulated structure may be greater at or near a centerline of the interposer opening than the encapsulant material thickness that would otherwise be required to properly encapsulate the wire bonds or other intermediate conductive elements that extend over regions of the surface of an interposer that are located adjacent a periphery of an opening formed therethrough. As a result, the overall height of a glop-top encapsulating structure may be undesirably high, providing an undesirably thick semiconductor device package.
Accordingly, there is a need for a method for encapsulating connections between an interposer and semiconductor die of a semiconductor device assembly that facilitates leak-free introduction of encapsulant from the backside of the semiconductor die and a resulting semiconductor device assembly.
SUMMARY OF THE INVENTION
The present invention includes a semiconductor device assembly packaging method and semiconductor devices packaged in accordance with the method.
A packaging method incorporating teachings of the present invention includes assembling a semiconductor die with a substrate element, such as an interposer or a carrier substrate, by disposing a two-sided adhesive tape or other substantially planar member with adhesive on at least portions of both surfaces thereof between the active surface of the semiconductor die and the backside of the substrate element. Bond pads of the semiconductor die are exposed through a slot formed in the tape, as well as through an opening formed through the substrate element and aligned with the slot. At least one end and, preferably, both ends of the slot formed through the tape extend beyond an outer periphery of the semiconductor die. It is preferred, however, that neither end of the slot extends beyond an outer periphery of the substrate element with which the semiconductor die is assembled.
Wire bonds or other suitable intermediate conductive elements (e.g., tape-automated bonds (TABs) or thermocompression bonds) may be formed between the bond pads of the semiconductor die and the corresponding contacts of the substrate element. Of course, these intermediate conductive elements extend through the slot of the tape and the opening of the substrate element.
A coverlay, such as a tape or other substantially planar member having a single side thereof coated with adhesive material, may be disposed over the exposed surface of the substrate element opposite the semiconductor die so as to cover the intermediate conductive elements extending through the substrate element. The coverlay preferably substantially seals the outer substrate element side of the opening formed by the slots of the substrate element and the tape. Thus, the intermediate conductive elements are substantially contained by interior lateral edges of the substrate element and the tape, as well as by the semiconductor die and the coverlay, the only exception being that one or both ends of the slot formed through the tape may be exposed beyond the outer periphery of the semiconductor die. The coverlay may also include one or more recessed areas that are configured to receive
Chai Lee Kian
Hui Chong Chin
Pittam Jason
Micro)n Technology, Inc.
TraskBritt
Vigushin John B.
LandOfFree
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