Method for enabling concurrent misses in a cache memory

Details Method for enabling concurrent misses in a cache memory Method for enabling concurrent misses in a cache memory

1994-12-01

1997-06-03

Chan, Eddie P.

395460, G06F 1208, G06F 1314

Patent

active

056363648

ABSTRACT:
In a cache-to-memory interface, a means and method for timesharing a single bus to allow the concurrent processing of multiple misses. The multiplicity of misses can arise from a single processor if that processor has a nonblocking cache and/or does speculative prefetching, or it can arise from a multiplicity of processors in a shared-bus configuration.

REFERENCES:
patent: 4794521 (1988-12-01), Ziegler et al.
patent: 4916604 (1990-04-01), Yamamoto et al.
patent: 4964041 (1990-10-01), Jeremiah et al.
patent: 5455924 (1995-10-01), Shenoy et al.
IBM Technical Disclosure Bulletin, "A Protocol for Processing Concurrent Misses", Dec. 1993, vol. 36 No. 12.
IBM TDB vol. 25 #11B Apr. 1983 "Design for Improved Cache Performance via Overlapping of Cache Miss Sequences" G. Driscoll et al pp. 5962-5966.
IBM TDB vol. 22 #12 May 1980 "Using a Branch History Table to Prefetch Cache Lines" R. Rechtschaffen p. 5539.
IBM TDB vol. 32 #7 Dec. 1989 "Cache Miss Leading Edge Processing" Puzak et al pp. 274-275.

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