Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2007-05-29
2007-05-29
Shah, Kamini (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C700S097000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
10225215
ABSTRACT:
The invention relates to a method for eliminating routing congestion in an integrated circuit (IC) layout defined by a placement plan indicating a position within the layout of each cell forming the IC and routing plan describing routes followed by nets interconnecting the cells. Routing congestion is eliminated by estimating routing congestion in various areas of the layout and relocating each cell to least routing congested areas of the layout for which cell relocation results in a reduction in the total lengths of the nets connected to the cell that exceeds a predetermined minimum reduction.
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Cadence Design Systems Inc.
Patel Shambhavi
Rosenberg , Klein & Lee
Shah Kamini
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