Semiconductor device manufacturing: process – Semiconductor substrate dicing
Reexamination Certificate
2000-11-21
2002-12-10
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
C438S658000, C438S719000, C438S680000, C501S087000, C257S639000
Reexamination Certificate
active
06492247
ABSTRACT:
TECHNICAL FIELD
This invention generally relates to methods of manufacturing integrated circuits (“IC”), memory circuits or memory chips. More particularly, this invention relates to a method for manufacturing ICs to manage crack damage and propagation especially where the crack damage is induced by the delamination of the gate conductor surface interfaces during the IC wafer dicing process.
BACKGROUND OF THE INVENTION
The full-scale production of ICs or other types of chips that are fabricated on wafers involves the forming of many individual ICs on the wafer and then separating the ICs by a dicing or cutting process. The fabrication of ICs may be completed through different methods and steps, but generally involves depositing layers of conducting, semiconducting and insulating materials in precise patterns on a substrate or wafer to form the desired circuit or array patterns. The dicing process is required to separate the individual ICs from the wafer.
It is during this dicing step that delamination, scalloping or cracking of some of the layers deposited on the wafer may occur as a result of the vibration and impact forces imparted to the wafer. Even if cracks are not directly produced in the wafer by the dicing process, the delamination or scalloping of the wafer layers may later lead to the development of cracks in the, or in between the, wafer layers. In particular, cracks may be produced in the wafer substrate or the conductive layer deposited in the dicing channel formed between the individual ICs.
If cracks develop in the IC during the dicing process, or propagate into the IC after the dicing process, the functional performance of the chip may be affected. More particularly, if a crack formed in the wafer or conductive layer propagates into the active array or circuit, functional performance will likely be adversely affected. For example, if a crack propagates into the IC, the active array or the circuit, fatigue failures or separation failures of the IC layers may result. Separation failures may in fact include a layer or layers of the IC breaking off. Obviously, such failures may compromise the electrical performance of the chip and are unacceptable.
While propagation of a crack within the IC during the dicing process is an issue, crack propagation after the completion of the dicing process can also occur as a result of testing of the IC. For example, thermal cycling tests, which are standard reliability tests conducted on ICs, may induce crack propagation. Similarly, crack propagation can occur as a result of packaging of the ICs. These later failures are problematic because while the chip may appear functional after initial separation from the wafer, it may later fail due to propagation of the crack into the chip active circuit.
Several mechanisms to stop or control the propagation of cracks within ICs are available and used in the manufacturing of ICs. The traditional method to control cracks is through the use of crack stops in the form of air gaps or filled gaps specifically designed into the IC layered structure. Air gaps are simply the creation of perimeter voids or air channels in the IC, which serve as natural termination points for edge cracks propagating within the solid dielectric material or between the metal wiring and the dielectric material. Air gaps, if deep enough, can prevent the horizontal propagation of any edge crack in the IC device, including cracks arising from delamination of the gate dielectric. However, typical dry etch process integration requires or may require the air gap to be terminated on top of the gate conductor. The resulting air gap is then ineffective in stopping cracks caused by delamination in the upper films of the gate conductor.
Filled gaps are perimeter walls of metal wiring material, which also serve as blocking or termination points for edge cracks. In order to make a metal-filled gap, the IC wiring on both the active and kerf side must, by design, not extend up to the gap. The resulting metal wall may then be effective in stopping edge cracks which propagate in the intervening dielectric materials. However, if the metal-filled gap is built on top of the gate conductor, as typical IC processing requires, it will be ineffective in stopping horizontal cracks which develop within the gate conductor, for example by delamination of the surface films. Moreover, it has been found that even if the gate conductor is pulled back by design, if it is not pulled back far enough, a crack propagating from the end of the gate conductor may still pull apart the metal, enter the active array of the chip, and cause failure. This is particularly the case when the metal wall is comprised of dissimilar metal wiring elements stacked on top of each other, such as aluminum and tungsten.
Two examples of processes and designs for controlling cracks in ICs are U.S. Pat. Nos. 5,530,280 and 5,665,655, both disclosing a Process For Producing Crackstops On Semiconductor Devices And Devices Containing The Crackstops, both being issued to White and assigned to the Applicant. Both White patents disclose processes for producing metal-filled gaps and, by subsequent etch removal of the metal, air gaps. FIG. 20 in the '655 White patent shows a typical metal-filled crackstop, which is built on top of the silicon substrate. The active device area typically contains a gate conductor, but there is no teaching about whether that gate conductor may extend under the crackstop, if the gate conductor must be removed from below the crackstop prior to building the crackstop, or if removed, how far away it must be from the crackstop. Indeed, because the entire scope of the two White patents is how to form metal-filled crackstops, the gate conductor layer is not even shown in any of the White patents figures. FIG. 24 shown in the '655 White patent shows an air gap or air channel crackstop produced by etch removal of the previously described metal wall. As noted, there is no teaching in the '655 White patent about the gate conductor layer on the substrate.
Similarly, FIG. 25 in the '655 White patent shows an air gap plus metal wall embodiment which would be effective in stopping horizontal cracks in the gate conductor if the gate conductor layer were present on the substrate in the kerf area. However this example, and indeed all air gap examples of the two White patents, are impractical because they require a complex sequence of etch steps to remove the different metals, including typically aluminum and tungsten, which comprise the outer or kerf-side metal wall, and which becomes an air gap. It is further impractical because, as more and more wiring levels are added to IC technologies, it becomes less and less feasible to etch out a high aspect ratio metal wall.
Another method for controlling crack propagation in ICs is disclosed in U.S. Pat. No. 5,789,302, entitled Crack Stops, issued to Mitwalsky et al., and also assigned to the Applicant. The Mitwalsky et al. invention teaches a method of forming crack stops in ICs for substantially preventing cracks produced along the dicing channel from spreading into the IC active area. The crack stops described are formed by creating discontinuities in the thickness of the dielectric layer in the dicing channel near the IC edges. According to Mitwalsky et al., the discontinuities can be formed by increasing and/or decreasing the thickness of the dielectric layer.
While Mitwalsky et al. do disclose a method of controlling crack propagation originating from within the dicing channel, the method does not appear to specifically address the problem of cracks that develop from delamination of wafer layers within the dicing channel. More significant, while Mitwalsky et al. disclose the use of discontinuities formed in the dicing channel near the edge of the IC active array, there is no teaching about the dimensions or geometry of the discontinuity, especially as related to the IC height. It has been discovered, for example that the formation of a discontinuity very close to the edge of the IC active array may not preve
Guthrie William H.
Kluwe Andreas
Ruprecht Michael
Rocchegiani Renzo N.
Smith Matthew
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