Semiconductor device manufacturing: process – Direct application of electrical current
Reexamination Certificate
1999-01-12
2001-03-06
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Direct application of electrical current
C216S017000
Reexamination Certificate
active
06197664
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the plating of conductive material onto a substrate during the fabrication of semiconductor devices, and more specifically, to methods for plating conductive material in through holes and blind apertures of a substrate having conductors on both its upper and lower surfaces.
2. Description of the Prior Art
In fabrication of printed circuit boards (PCBs) and multi-chip modules (MCMs), it is often desired to plate the inside surfaces of a through-hole or blind aperture formed in a substrate with a conductive material. Once the conductive material is plated, a through hole is often referred to as a through via, and a blind aperture is often referred to as a blind via. Through vias are used to connect electrical traces which are on opposite sides of a PCB board or MCM substrate, and blind vias are used to connect electrical traces within the body of such board and substrates to one another and to traces on the surfaces of the board or substrate.
There is a demand in the semiconductor industry for an increasing density of electrical traces and interconnections, which often requires a high density of through vias and blind vias at smaller aperture diameters and higher aspect ratios (i.e., the ratio of length:diameter). In meeting this demand for higher trace and interconnection densities, it would be advantageous to be able to construct a structure formed from alternating conductive and dielectric layers before forming the apertures for the through vias and/or blind vias. In such a case, it would be desirable to fill the apertures with a conductive material (e.g., metal) by a plating process which used one of the conductive layers as the plating cathode. However, when it is attempted to use a conventional plating process to fill the apertures in this manner, it is found that the conductive layer(s) not acting as the cathode are etched away by the plating bath, which is usually acidic.
A possible solution to this problem is to mask the non-cathode conductive layers with a material which is resistant to the plating bath, e.g., photoresist. However, this requires additional processing steps to apply and remove the protective layer, and in many cases cannot be practically applied to the case where the alternating material layers are formed prior to the formation of the apertures.
What is desired is a method for plating through holes and vias formed in a substrate having a conductor on its top and bottom surfaces with a conductive material, which does not require a substantial increase in processing steps and which is compatible with the above-described multi-layer construction method.
SUMMARY OF THE INVENTION
The present invention is directed to a method for plating conductive material in through apertures and blind apertures of a substrate which has a conductive material or layer on its upper (top) and lower (bottom) surfaces. In a typical configuration for plating a via, there is a first region of conductive material adjacent to, but outside of, the aperture which forms the via and a second region of conductive material inside of the aperture, e.g., a portion of a conductive layer formed over the substrate. The second conductive region is selected to be the cathode of the plating process. The substrate/via structure is placed in a plating bath, a first potential is applied to the first region of conductive material, and a second potential is applied to the second region of conductive material, with the second potential being different from the first potential. Under these conditions, and with properly selected values for the first and second potentials, material will be selectively plated onto the second region of conductive material to fill the aperture. The value of the first potential is preferably selected to substantially reduce the rate at which the first region of conductive material is etched by the plating bath, and may be used to cause material to be plated onto first region, but at a slower rate than the plating of the second conductive region.
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Chou William T.
Lee Michael G.
Peters Michael G.
Coudert Brothers
Fujitsu Limited
Lee Calvin
Smith Matthew
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