Method for electroplating the lead pins of a semiconductor devic

Details Method for electroplating the lead pins of a semiconductor devic Method for electroplating the lead pins of a semiconductor devic

1992-08-27

1993-08-31

Chaudhuri, Olik

Electrolysis: processes, compositions used therein, and methods

Electrolytic coating

Coating selected area

205123, 437218, H01L 2160, C25D 1706, C25D 502

Patent

active

052405885

ABSTRACT:
A method for manufacturing a pin grid array type semiconductor device package including a substrate having a principle surface and a bottom surface opposing the principal surface, a plurality of patterned metallized conductors formed in the substrate or on the principal surface of the substrate so as to be electrically connected to a semiconductor device chip to be located on the principal surface. A plurality of metallized pads are formed on the bottom surface and electrically connected to the patterned metallized conductors. A metal film is deposited so as to cover the bottom surface including the metallized pads, and a lead pin is soldered on the metal film above each metallized pad by a solder material. The lead pin is electroplated by applying a voltage to the metal film.

REFERENCES:
patent: 4622106 (1986-11-01), Kitagawa
patent: 5022976 (1991-06-01), Roll et al.
patent: 5087331 (1992-02-01), Roll et al.

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