Method for electrically testing a semiconductor die using a test

Details Method for electrically testing a semiconductor die using a test Method for electrically testing a semiconductor die using a test

1993-02-08

1994-07-19

Chaudhuri, O

Fishing, trapping, and vermin destroying

324765, G01R 3126, H01L 2166

Patent

active

053309197

ABSTRACT:
A method for controlling a characteristic impedance during testing of a semiconductor die (13). The semiconductor die (13) is mounted in a TAB package (10 or 54 ) wherein the TAB package ( 10 or 54 ) lacks a ground plane. A conductive plate (40 or 70) is removably mounted to a test contact fixture ( 29 or 60 ) . The conductive plate (40 or 70) may be coated with a layer of dielectric material (50, 56, or 74) having a specified thickness. The layer of dielectric material (50, 56, or 74) contacts a plurality of conductive fingers (16). A microstrip transmission line is formed which includes the plurality of conductive fingers (16) , the layer of dielectric material (50, 56, or 74), and the conductive plate (40 or 70). The semiconductor die (13) is tested by a computer controlled automatic tester (28).

REFERENCES:
patent: 4763409 (1988-08-01), Takekawa et al.
patent: 5086269 (1992-02-01), Nobi
patent: 5087877 (1992-02-01), Frentz et al.

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