Metal fusion bonding – Process – Plural joints
Reexamination Certificate
2001-06-06
2003-04-22
Elve, M. Alexandra (Department: 1725)
Metal fusion bonding
Process
Plural joints
C228S180210, C228S245000, C257S738000
Reexamination Certificate
active
06550665
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming arrays of electrical interconnects between substrates. In particular, the present invention relates to a method of using a eutectic composition to form physical and electrical interconnects.
2.Description of the Background
In the fabrication of certain types of semiconductor devices it is desirable to mate one semiconductor device to another. The mated semiconductor devices may be of the same material or different materials, and are mated to physically attach the devices to each other. Additionally it may be desired to form a large number of electrical interconnects between the devices to allow electrical conduction of signals from one device to the other. An example of the use of this type of interconnect technology is in the area of modern state-of-the-art infrared components. In these devices one material is optimized to perform the detection function while another material is optimized to perform the function of detector biasing, signal integration, signal processing, and multiplexing. The interconnect arrays for these devices physically and electrically interconnect the infrared detector to the readout-integrated-circuit. For these devices it is desirable to form from one to millions of electrical interconnects between these materials.
Implementations of high-density indium bump interconnect technologies are described in, for example, U.S. Pat. No. 4,930,001 to Williams et al. and U.S. Pat. No. 5,186,379 to Helber et al. In these methods, the electronic interconnects are formed by first forming metallic bumps or pads on each substrate to be electrically connected, and then precisely aligning the device substrates and their respective interconnect bump arrays to one another. The bumps are then attached to each other using elevated temperatures to melt the bumps into each other, or elevated pressures to force solid bumps to bond in a process known as a “cold weld,” or by using a combination of elevated temperature and pressure. For example, U.S. Pat. No. 5,186,379 describes a cold weld method of forming of an intermetallic-free alloy between indium and a second metal such as aluminum, cadmium, gallium, germanium, silicon, or zinc in which pressures between 2000 and 6000 PSI are used to bond the bumps. A combination of elevated temperature and pressure has been used to bond indium bumps to gold pads, as described in U.S. Pat. No. 4,930,001. The indium bumps are pressed into the gold pads at a high pressure (800 PSI) for a short period of time to temporarily fuse the bumps. The fused bumps are then heated to an elevated temperature (100° C.) to melt and weld the indium and gold.
There are a number of problems with these and other methods used to electrically interconnect devices with bump bonding. In particular, for arrays containing a large number of interconnect bumps, it is necessary to use high pressures to cause the bumps to bond. Because the force required to mate and bond two arrays of bumps increases linearly with the number of bumps, as the bump density increases (or the area of the device increases for a given bump density), the force that must be used to form bonds between the devices must be increased. The increased force may exceed the strength of the materials to be mated and damage those materials and devices contained within them, reducing process yields and degrading the reliability of the devices.
High temperatures used for molten solder processes allow the bump contact to be made at very low pressures. However, the devices must be maintained at a very precise alignment during the thermal exposure cycle to prevent the bumps from cross-wetting the adjacent bumps. Additionally, if the mating substrate materials have dissimilar coefficients of thermal expansion, stresses introduced into the mating bumps as the device cools can also lead to substrate damage and device failure.
SUMMARY
A method is provided that allows for the use of large arrays of interconnects to physically and electrically mate two substrates without the need to use excessive pressure on the substrates, thus advantageously reducing the damage to substrates and improving yields. In one embodiment, an array of bumps is formed on a first substrate. The bumps are formed from a material that forms a eutectic composition with a second material. An array of bumps made from the second material is formed on a second substrate. The arrays of bumps on the first and second substrates are aligned and brought into contact with each other at a contact temperature, which is a temperature above the eutectic temperature of the eutectic composition formed by the two materials and typically below the melting temperatures of the two materials. The contacted bumps join to form joined bumps. The relative volumes of the bumps on the first substrate to the bumps on the second substrate can be used to control the phase of the joined bumps at the contact temperature. The substrates and joined bumps may then be cooled to below the eutectic temperature. An adhesive material may also be applied to interstices between joined bumps after mating and joining the bumps to provide additional mechanical support.
In one embodiment, a portion of the array of bumps on the first substrate is made of a different material than the first material. This portion of the array of bumps may be at the periphery of the array, and may be used, for example, to add structural support to the resulting array of electrical interconnects. In one embodiment, this portion of the array of bumps is made from indium and the rest of the bumps on the first substrate are formed from gallium. The array of bumps on the second substrate is also formed from indium.
In one embodiment, one of the substrates is an IR sensitive detector material and the other substrate is an integrated circuit readout chip and the method is used to form an infrared sensor device.
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Barton Jeffrey B.
Parrish William J.
Elve M. Alexandra
Indigo Systems Corporation
MacPherson Kwok & Chen & Heid LLP
Tran Len
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