Computer graphics processing and selective visual display system – Computer graphic processing system – Integrated circuit
Reexamination Certificate
1998-08-06
2001-03-20
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphic processing system
Integrated circuit
C345S440000, C345S519000, C711S136000
Reexamination Certificate
active
06204863
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to graphics processors, more specifically, the present invention relates to the rasterization of graphics data to host memory using display list processing.
BACKGROUND OF THE INVENTION
The use and application of computer graphics to an increasing number of systems environments continue to grow. This growth has been accelerated to an even greater extent with the availability of faster and faster information processing, storage, memory and retrieval devices. The speed of operation of such devices remains a high priority design objective. This is especially true in a graphics system and even to a greater extent with 3D graphics systems. Such graphics systems require a great deal of processing for huge amounts of data and the speed of data flow is critical in providing a new product or system or in designing graphics systems to apply to new uses.
Many methods exist in computer graphics environment to present information on a graphics display device. One of such methods is using polygons to draw graphics primitives such as lines and objects. The polygons may generally be reduced into a series of scan lines which align to the edges of the polygon and to a pixel grid. The pixel grids are generally accessed in a sequential manner i.e., XY addressing. Each accessed pixel grid is then textured with a variety of texture maps.
In addition to the basic position and color parameters, graphics controllers are available which permit the texture of polygons to be represented as part of the display. A texture may be defined as an image of a pattern generated by the graphics processor.
Texture mapping is a computer graphics technique which comprises a process of overlaying a source texture on to a polygon surface to add realism to computer generated three dimensional images. It enhances the visual reality of raster scan images substantially while incurring a relatively small increase in computational time. In general, texture mapping allows a multidimensional image to be mapped to a multidimensional space by taking into account the perspective of the mapping algorithm. A texture may, for example, be thought of such as a sandpaper, a roadbed and so forth or as the pattern of pixels (picture elements) on a sheet of paper. The pixels may be arranged in a regular pattern such as a checkered board or may exhibit high frequencies as in a detailed photograph of high resolution.
While a pixel grid stored in memory is represented by a two dimensional space in a linear accessed memory, perspective mapping of texture maps often results in the texel samples to move through the texture map in a nonlinear fashion. As a polygon is being rendered in X space (walking an ortho span) on a display screen, the texel samples will be moving in both U and V space in memory. Thus, in order to achieve fast texture mapping, the memory type used for texture mapping storage must have low latency for random access.
Most graphics subsystems store texture maps in main system memory. Storing the maps in main memory may require a graphics drawing engine to access the texture maps via a bus external to the graphics processor. Each such access and transfer of the texture maps results in processing delays due to inherent memory latency. These latencies substantially slow down the rate at which the graphics processor can therefore process the texture maps.
To alleviate the processing load and data throughput experienced by the system bus, some very high end texture mapping engines use either large internal static random access memory (SRAM) internal buffers or high speed external SRAMs for storing the texture maps. However, many of these low end texture map engines may only make use of a small part of their frame buffer for texture map storage. This is usually some form of DRAM technology which with poor random access rate does not solve the slow processing rates of the texture maps.
Prior art texture map engines which utilize large external SRAM buffers offer excellent random access rate of texel per system clock rate. However, these engines experience real estate constraints as a result of the large internal SRAMs which tend to occupy a large die area and consequently prove to be very costly. For example, in order for the texture map engine to store 256×256×16 bpp, the internal SRAM buffer would have to be at least 128 Kbytes.
Another method used in the prior art to store texture maps is to have an external SRAM or DRAM to store the texture maps. Having an external SRAM provides a good random access rate, however, this method of storing can still be very costly due to high SRAM prices. Furthermore, the access rate to the external SRAM banks is about half of that of internal SRAM. This may be because the texture engine has to pass addresses and receive data from sources external to the graphics processor.
An external DRAM, on the other hand, provides good sequential access and is less expensive than an SRAM, but has long latency for random accesses. Since real texture mapping applications are going to be rendering in both U and V space, the random access penalty experienced by using external DRAM storage means often results in poor overall system performance.
The above illustrated problems become even worse when using a Rambus based DRAM (RDRAM) for texture storage. Although RDRAMs have excellent burst data rate of approximately 528 Mbytes/Sec, they also have a substantial random access rate due to the long latency which may be approximately 3 Mbytes/sec. The problem with poor random reads becomes even worse if the host computer's system main memory is used for texture map storage. Accessing system main memory requires arbitrating for the system bus (e.g., PCI bus) and a subsequent arbitration for shared memory resources in the host system. There is also a standard penalty of random access to a DRAM based memory system which may be experienced by the texture map engine. This obviously results in very long memory latency and poor random access.
The architectural challenges therefore presented by texture mapping and texture map storage is that of distributing the processing load to achieve better system performance. Thus, what is needed is a graphics processor which effectively stores texture maps which may be efficiently accessed by the graphics drawing engines without incurring any of the inherent random access latency problems experienced in using external memory storage devices. A system is also desired which allows the graphics processor to take advantage of the high burst rates of system buses such as the PCI bus and high bandwidth memory devices, such as RDRAMs, in retrieving texture maps from the texture engines to the drawing engines.
SUMMARY OF THE INVENTION
An improved graphics information storage method and apparatus is provided which stores graphics texture maps internal to a graphics processor to enable fast storage and retrieval to a graphics drawing engine. The present invention includes internal cache storage units for storing texture maps and an internal cache controller for controlling the internal cache units. The texture map is cached internal to the graphics processor as UV tiles of the texture map. The internal SRAM memory is divided into a number of cache tiles (ways). Each cache tile is capable of holding a UV section (tile) of texture memory. The internal cache controller is capable of doing UV tile read hit comparisons and subsequent UV to linear address conversions to read the texel from The SRAM.
The internal cache controller is also capable of generating the UV tile fetch request to an XY memory controller. Caching UV tiles allows the graphics processor to take advantage of the high burst rate fills to load the cache ways. These tile fetches happen at the burst access rate of the memory technology. By caching a UV tile, the likelihood of the next texel fetch being a cache hit is very high. Anytime the texel is in internal cache, the access is zero wait state. Caching texture memory in UV tiles is required due to the nature of consecut
Cirrus Logic Inc.
Lin Steven
Rutkowski Peter T.
Tung Kee M.
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