Method for driving thin film transistor of liquid crystal...

Details Method for driving thin film transistor of liquid crystal... Method for driving thin film transistor of liquid crystal...

1999-08-27

2001-11-13

Wu, Xiao (Department: 2674)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

C345S094000

Reexamination Certificate

active

06317113

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for driving a thin film transistor (TFT), and more particularly, a method for driving a thin film transistor of a liquid crystal display (LCD).
BACKGROUND OF THE INVENTION
FIG. 1
shows a TFT, and
FIG. 2
is a circuit diagram thereof. When a voltage V
g
applied to a gate of the TFT exceeds a threshold voltage V
TH
, a drain and a source are conductive and a current I
d
is flown therebetween.
FIG. 3
shows a curve of gate voltage V
g
versus current I
d
. In the case of repeated usage of the TFT, a problem of drift of the threshold voltage V
TH
is produced, referring to FIG.
3
. The relationship between the drifted voltage difference &Dgr;V
Th
and gate-source voltage V
gs
is shown in FIG.
4
. Namely, the voltage difference &Dgr;V
TH
is increased as voltage stress caused by the gate-source voltage V
gs
is increased. The drift problem of the threshold voltage is particularly serious in the case of amorphous silicon TFT (a-Si TFT) formed by low temperature chemical vapor deposition (CVD).
FIG. 5
shows an architecture of an active matrix LCD using TFTs. A TFT is provided at each intersection of data signal lines DL and scanning lines GL. The TFT has a gate connected to the scanning line GL, a source connected to the data signal line DL, and a drain connected to a liquid crystal capacitor C
LC
. A gate driving unit
20
sequentially provides each of the scanning lines with a gate scanning pulse voltage V
g
to sequentially select one corresponding gate line GL. When the gate scanning pulse voltage V
g
is applied, the TFT on the corresponding gate line GL is on. A data driving unit
10
provides each of the data signal line DL with an image signal V
d
.
FIG. 6
is a timing chart showing a conventional N-channel TFT in which a voltage V
d
is applied to a gate scanning line. Time t
0
to t
3
, t
3
to t
5
, t
5
to t
7
, . . . each is a field pen rod time T
2
. In a field time, all the gate lines GL are sequentially scanned by the gate scanning unit
20
. Time t
0
to t
1
, t
3
to t
4
, and t
5
to t
6
each is a horizontal selection period (horizontal scanning period) T
1
. In T
1
, V
g
is at high level (V
gH
). In this case, a transistor on the gate scanning line is turned on and the image signal V
d
on the data signal line is written to a liquid crystal capacitor C
LC
. In non-horizontal scanning time T
3
, V
g
is at low level (V
gL
). In this case, the transistor on the gate scanning line has a high impedance, which prevents the image signal V
d
on the liquid crystal capacitor C
LC
from leakage. The image signal is a NTSC video signal consisting of two interleaved field signals. A frame image is composed of two fields. A field time is {fraction (1/60)}second. That is, T
2
=16.7 ms. As to T
1
, it depends on the number of scanning lines, it is equal to 63.5 &mgr;s in the case of 480 scanning lines.
FIG. 7
shows an ideal relation between voltages of a gate, source and drain of a TFT and voltage V
gs
at the initial moment of gate scanning pulse voltage V
g
between two field times (i.e., instants of on and off of the transistor).
FIGS. 7A and 7B
show voltage variations when t=t
0
and t=t
1
, respectively. Since the voltage V
d
applied to the gate of the transistor is +V
D
, such a field is referred to as positive field. In this case, V
gs
=V
gH
−V
D
, and drain voltage is charged from −V
D
on the liquid crystal capacitor C
LC
to +V
D
.
FIGS. 7C and 7D
show voltage variations when t=t
3
and t=t
4
, respectively. Since the voltage V
d
applied to the gate of the transistor is −V
D
, such a field is referred to as negative field. In this case, V
gs
=V
gH
+V
D
, and drain voltage is discharged from +V
D
on the liquid crystal capacitor C
LC
to −V
D
. In both cases, there is a difference of 2V
D
, which readily causes a variation in electric field stress and thus &Dgr;V
TH
is produced.
FIG. 8
shows variation of the liquid crystal capacitor C
LC
in a frame period. In the horizontal selection time of the positive field (t=t
0
~t
1
), the image signal V
d
is +V
D
, and thus the liquid crystal capacitor C
LC
starts to charge. When the scanning pulse ends, the TFT is turned off and the charge is maintained on the liquid crystal capacitor C
LC
. In the horizontal selection time of the negative field (t=t
3
~t
4
), the image signal V
d
is −V
D
, and thus the liquid crystal capacitor C
LC
starts to discharge. When the scanning pulse ends, the TFT is turned off and the charge is maintained on the liquid crystal capacitor C
LC
. However, at the moment when the transistor is turned off, a voltage drop of &Dgr;V
d
is produced on the liquid crystal capacitor C
LC
. The quantity of &Dgr;V
d
depends on stray capacitance C
GD
between the gate and the drain of the TFT, the liquid crystal capacitance, and voltage variation of scanning line &Dgr;V
g
=(V
gH
−V
gL
) Namely, &Dgr;V
d
+
=&Dgr;V
d
−=&Dgr;V
d
=[C
GD
/(C
GD
+C
LC
)]×&Dgr;V
g
. Such a voltage drop (shifted voltage) is irrelevant to polarity of the image signal. Therefore, according to the prior art, a common electrode potential V
COM
of a color filter is set to be lower than the central potential of the signal line by such a shift value, so that the voltage applied on the liquid crystal is symmetric with respect to the origin except at the charging time and discharging time.
However, since dielectric coefficient of an actual liquid crystal is anisotropic, capacitance of the liquid crystal capacitor C
LC
and the shift voltage &Dgr;V
d
are varied due to amplitude of the image signal. Therefore, even the common electrode potential V
COM
is optimized, the voltage applied on the liquid crystal is asymmetric. Such an asymmetric component is an optical component of 30 Hz, and flicker phenomenon is observed. To avoid flicker, the shift voltage &Dgr;V
d
is minimized. To this end, the TFT is minimized and a holding capacitor C
ST
is connected to C
LC
in parallel, such that &Dgr;V
d
=[C
GD
/(C
GD
+C
LC
+C
ST
)]×&Dgr;V
g
. Such a shift voltage &Dgr;V
d
is equivalent to D.C. potential between the signal line and pixel electrode. When a D.C. potential exists in a liquid crystal layer, a residual image is generated, thereby reducing reliability of the liquid crystal. Therefore, &Dgr;V
d
must be minimized to obtain high picture quality and high reliability.
Nevertheless, due to restrictions of TFT manufacture, it is difficult to decrease the stray capacitance C
GD
. Thus, the best way is to increase capacitance of the holding capacitor C
ST
, which reduces open ratio of the liquid crystal display, and makes structure thereof complicated.
SUMMARY OF THE INVENTION
An object of the present invention is to set forth a method for driving TFTs in a LCD in which a shift voltage of a central voltage level of liquid crystal capacitors connected to the TFTs is reduced to enhance uniformity of the LCD.
Another object of the present invention is to provide a method for driving TFTs in a LCD in which the TFTs have lower holding capacitances to enhance open ratio of the LCD.
A further object of the present invention is to provide a method for driving TFTs in a LCD in which the TFTs of the LCD are not readily influenced by an electric field and thus the voltage stress caused is reduced.
To achieve the above objects, the present invention provides a method for driving a TFT wherein voltage for driving a gate is changed such that peak values of the gate pulse voltage in a first field and a second field are not equal, and the difference therebetween is not larger than double of voltage peak value of a image data. Therefore, voltage reduction of a liquid crystal capacitor can be decreased without enlarging the capacitance thereof. Further, since the gate voltage applied is smaller in a half of each period, the TFT of the LCD is less influenced by an electr

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