Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-01-22
2002-06-04
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
Reexamination Certificate
active
06400347
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for driving sustain lines for a white balance in a plasma display panel, and more particularly to a method for driving sustain lines in a plasma display panel, in which when the white balance is adjusted considering the characteristic of the panel, an erase pulse is inserted by the color in the period in which the sustain pulse is applied, so that the pulses of a ratio required in good white balance can be applied.
For example, a plasma display device, one of flat panel displays, has a plasma display panel (PDP) of luminous element and displays image sequence or still picture by using the gas discharge phenomenon in the PDP
FIG. 1
shows a cell structure in a general plasma display panel. In the figure, the PDP has an upper glass substrate
1
, i.e., the surface on which picture is displayed, a lower glass substrate
2
disposed in parallel with the upper glass substrate
1
by a predetermined distance, a barrier rib
3
arranged between the upper glass substrate
1
and the lower glass substrate
2
to form a discharge space, a scan electrode
4
and a common electrode
5
(hereinafter, referred to as “first and second sustain electrodes”) alternately arranged on the surface of the upper glass substrate
1
facing the lower glass substrate
2
to be directly crossed with the barrier rib
3
, a dielectric layer
6
formed below the surface of the upper glass substrate
1
facing the lower glass substrate
2
to limit the discharge current, an address electrode
7
formed on the surface of the lower glass substrate
2
facing the upper glass substrate
1
between the barrier ribs
3
to generate a discharge together with the first and second sustain electrodes
4
and
5
, a phosphor layer
8
which is formed on the lower glass substrate
2
, the barrier rib
3
and the address electrode
7
in the discharging space and emits visible light of the phosphor
8
red, green and blue(R, G, B) at the discharge of each cell.
The PDP structured as described above generates the visible light by exciting the phosphor material to the ultraviolet rays emitted at the discharge between the electrodes, and such a discharge will be described with reference to
FIGS. 2 and 3
.
FIGS. 2 and 3
show the driving wave forms applied to each electrode and the wall charge processing states of corresponding cell according to the driving wave forms.
In embodying the grey level of a picture element, a cathode-ray tube (CRT) can adjust the brightness by using the strength of an electron beam, while the PDP embodies the grey level by the number of discharge per unit time because of the difficulty of adjusting the strength of discharge.
One picture element is composed of three discharge cells of R, G and B. In the case of 256 grey levels, if the discharge number of each cell is divided into 0~255 every frame, the brightness of 256 grey levels can be embodied according to the discharge number.
The discharges selectively occurred in each cell are composed of an address discharge for addressing a luminous picture element, a sustain discharge for sustaining the discharge of the cell and an erase discharge for stopping the sustaining of the discharge cell.
Here, the wall charge is formed on the dielectric layer
6
near the first and second sustain electrodes
4
and
5
in the discharge space by the address discharge between the address electrode
7
of the lower glass substrate
2
and the sustain electrodes
4
and
5
of the upper glass substrate
1
, and is sustained by the sustain discharge between the first and second sustain electrodes
4
and
5
of the upper glass substrate
1
.
If the driving wave forms shown in
FIG. 2
are applied to the electrodes
4
,
5
and
7
, the processing states of the wall charge in the sections (a) to (h) are shown as states (a) to (h) in FIG.
3
.
That is, there was no wall charge in the discharge cell before the state (a) of FIG.
3
. If there occurs an address discharge between the address electrode
7
and the first sustain electrode
4
in the section (a), there forms the wall charge in the cell at the section (b) after the address discharge.
In this case, most of the wall charge are formed at the first and second sustain electrodes
4
and
5
. The write pulse applied to the address electrode
7
has a width of over 2 &mgr;s and this width corresponds to the time required in forming the wall charge.
There occurs the sustain discharge between the first and second sustain electrodes
4
and
5
at the section (c), and after the sustain discharge, the wall charge opposite to that at the section (b) is formed at the section (d).
In this case, the sustain voltage of the electrodes
4
,
5
and
7
may be lower than the difference of the write voltage between the address electrode
7
and the sustain electrode
4
. This is because of the wall charge formed on the dielectric layer
6
and there occurs no sustain discharge at the cell having no wall charge.
At the sections (e) and (f), there occurs a sustain discharge by the sustain pulse and the wall charge opposite to that at the section (d) is formed.
Hence, one sustain period is from the section (c) to the section (f), and the discharge number during one sustain period is
2
.
The erase discharge occurs at the section (g) of
FIG. 3
by the erase pulse of FIG.
2
. And the erase pulse has a width of less than 1 &mgr;s and the voltage of the erase pulse is lower than that of the sustain pulse. There occurs a discharge between the first and second sustain electrodes
4
and
5
by this erase pulse, but the cell has no wall charge at the section (h) because there was no time to form the wall charge, and thus there occurs no discharge even though the sustain pulse is applied.
FIG. 4
shows a driving circuit of a general plasma display panel. The driving circuit comprises a PDP
10
having
640
R, G and B address electrode lines (R
1
, G
1
, B
1
, . . . R
6
40
, G
640
, B
640
) and
480
first and second sustain electrode lines (S
1
, S
2
, S
479
, S
480
), a microprocessor
20
of digitalizing the R, G and B picture data applied from the exterior and outputting R, G and B digital picture data of 8 bits (2
s
=256 grey levels) and various control signals required in driving the PDP
10
according to the external signal, a scanning and sustain driver
30
for applying a scan pulse to the first and second sustain electrode lines (S
1
~S
480
) according to the control of the microprocessor
20
to sequentially scan the lines and applying the sustain pulse to all of the first and second sustain electrode lines (S
1
~S
480
) to sustain the discharge and luminescence of each cell, a memory
40
for storing the R, G and B digital picture data of the microprocessor
20
by the frame, the color and the bit, and an address driver
50
for reading the bit values of 640 R, G and B digital picture data corresponding to the first and second sustain electrode lines S
1
~S
480
from the memory
40
by the scanning of the scanning and sustain driver
30
and applying the bit values to 640 R, G and B address electrode lines R
1
~B
640
.
The scanning and sustain driver
30
has a clock and data generator
31
for generating a clock CLK and data according to the control of the microprocessor
20
, a sustain pulse generator
32
for generating the sustain pulse according to the control of the microprocessor
20
, and a driving logic unit
33
for sequentially applying the scan pulse and the sustain pulse to the first and second sustain electrode lines S
1
~S
480
according to the clock, data and sustain pulse.
A description will be made on the process of displaying picture of 256 grey levels on the panel according to an address-display-separating (ADS) sub-field method with reference to
FIGS. 1
to
3
.
In the ADS sub-field method, for the embodiment of 2
s
grey levels, 1 frame of screen is displayed by being divided into X sub-field screens and the picture data applied from the exterior are digitalized into X bits of digital picture data (least significant bit(D
1
)~
Fleshner & Kim LLP
LG Electronics Inc.
Piziali Jeff
Shalwala Bipin
LandOfFree
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