Method for driving solid-state image sensing device

Television – Camera – system and detail – Solid-state image sensor

Reexamination Certificate

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Details

C348S324000, C348S322000, C377S063000

Reexamination Certificate

active

06683647

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for driving a solid-state image sensing device, and more particularly, to a method for driving a CCD solid-state image sensing device which is driven by a multiple-phase clock.
2. Description of the Related Art
Hitherto, a typical method for driving a solid-state image sensing device, that is, a method for driving a CCD solid-state image sensing device, generally employs driving control of electrodes with the driving timing shown in FIG.
6
.
Electrode terminals V&phgr;
1
, V&phgr;
2
, and V&phgr;
3
which are shown in
FIG. 6
are the terminal names of the electrode terminals connected to three kinds of poly-Si electrodes for forming a packet of V-CCDs (vertical-transfer charge coupled devices).
Also, clock voltage waveforms &phgr;
1
, &phgr;
2
, and &phgr;
3
are the voltage waveforms which are applied to each of the poly-Si electrodes described above via the above-described electrode terminals V&phgr;
1
, V&phgr;
2
, and V&phgr;
3
.
The amount of charge which can be handled by the V-CCD (hereinafter, referred to as “QV”) is determined by the packet size of the V-CCD described above.
FIG. 7
is a timing chart which shows a driving timing of a conventional CCD solid-state image sensing device.
In
FIG. 7
, symbols A to F show control intervals for forming potential wells in the V-CCD.
The control interval for forming a potential well is defined, more specifically, as an interval indicated by a period of time starting from the state in which three-phase clocks &phgr;
1
, &phgr;
2
, and &phgr;
3
are applied to the electrode terminals V&phgr;
1
, V&phgr;
2
, and V&phgr;
3
, respectively, while maintaining certain voltage levels, for driving the V-CCD described above via the electrode terminals V&phgr;
1
, V&phgr;
2
, and V&phgr;
3
, to the state when a change occurs (that is, a change occurs in one of the voltage levels of the above-described three-phase clocks &phgr;
1
, &phgr;
2
, and &phgr;
3
).
Hitherto, the length of a control interval (that is, the length of time) for which certain values of the voltage level of the three-phase clocks &phgr;
1
, &phgr;
2
, and &phgr;
3
are applied to the terminals V&phgr;
1
, V&phgr;
2
, and V&phgr;
3
is always constant for all the control intervals A to F.
In this regard, as the circumstances regarding CCDs in general, currently, there is a strong demand for a larger number of pixels, and therefore it becomes necessary to miniaturize a unit cell which constitutes a CCD.
However, in the conventional method for driving V-CCDs as shown in the
FIG. 6
described above, each control interval has the same length, and the electrode of the CCD which is located at end part has a longer wiring line than the other electrodes based on the structure of the electrode terminal when viewed from the input side of a clock signal at a certain timing, thus a delay occurs in the propagation time of the clock input with that timing.
Also, as shown in
FIG. 3
, the electrode has a complicated structure in which three kinds of electrodes are laminated with each other.
For this reason, impedance differences occur among the individual electrodes, thereby producing differences in the time constant among the individual electrodes. Consequently, in this case, QV described above is determined by the electrode having the largest time constant: thus there has been a problem in that a large QV cannot be ensured.
Moreover, by miniaturizing the unit cell size as described above, the area of the V-CCD becomes smaller. Thus, in addition, there has been a problem in that a large QV cannot be ensured because of this point.
In this regard, when a large QV is not ensured, the output image appears to have little reality, thereby causing a serious problem in the image quality of the solid-state devices.
SUMMARY OF THE INVENTION
Accordingly, the present invention is made in view of the above-described problems in the conventional method for driving a solid-state image sensing device, and an object is to provide a method for driving a solid-state image sensing device which can ensure handling of a sufficiently large charge.
In order to solve the above-described problem, in the present invention, there is provided a method for driving a solid-state image sensing device in which a plurality of charge coupled devices are arranged on a semiconductor substrate, including: performing control such that the length of a control interval starting from a point in time when a predetermined driving voltage is applied to an electrode having the largest time constant among a plurality of electrodes corresponding to the charge coupled devices is more than the length of any other control interval.
Specifically, in the present invention, in order to eliminate the influence of delay in the rise time of the driving voltage at the electrode which has the largest time constant (for example, an electrode having the longest wiring line as viewed from the input side of the driving clock, or an electrode laminated at the lowest layer) because of the structure of a CCD solid-state image sensing device, driving control is performed such that the length of a control interval (length of time) which starts from a point in time when a driving voltage is applied to the above-described electrode is more than the length of any other control interval. Thus, by setting a time period until the effective swing of the electrode described above is settled within a predetermined fixed value, it is possible to ensure a sufficiently large charge to be handled by the CCDs.


REFERENCES:
patent: 3758794 (1973-09-01), Kosonocky
patent: 3955100 (1976-05-01), Takahashi et al.
patent: 4112456 (1978-09-01), Lampe et al.
patent: 4554675 (1985-11-01), Miwada
patent: 4583003 (1986-04-01), Kimata
patent: 4980771 (1990-12-01), Ueda et al.
patent: 5051832 (1991-09-01), Losee et al.
patent: 5229857 (1993-07-01), Taniji
patent: 5847758 (1998-12-01), Iizuka
patent: 6075565 (2000-06-01), Tanaka et al.

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