Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-01-03
2002-03-05
Liang, Regina (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S063000
Reexamination Certificate
active
06353423
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for driving a plasma display panel, and more particularly, to a method for driving a plasma display panel, by which gray-scale display is achieved in a unit frame by a plurality of subfields in each of which an address step, a sustaining discharge step and a reset step are performed.
2. Description of the Related Art
FIG. 1
shows a general plasma display panel,
FIG. 2
shows an electrode line pattern of the plasma display panel shown in
FIG. 1
, and
FIG. 3
shows an example of a pixel of the plasma display panel shown in FIG.
1
. Referring to the drawings, address electrode lines A
1
, A
2
, A
3
, . . . , A
m−2
, A
m−1
and A
m
, a dielectric layer
11
(or
141
of FIG.
3
), scan electrode lines Y
1
, Y
2
, . . . Y
n−
and Y
n
, common electrode lines X
1
, X
2
, . . . , X
n−1
and X
n
, and a magnesium oxide (MgO) layer
12
as a protective membrane are provided between front and rear glass substrates
10
and
13
of a general surface-discharge type plasma display panel
1
.
The address electrode lines A
1
, A
2
, A
3
, . . . , A
m−2
, A
m−1
, and A
m
are disposed on the front surface of the rear glass substrate
13
in a predetermined pattern. A phosphor (
142
of
FIG. 3
) is disposed on the front surface of the scan electrode lines Y
1
, Y
2
, . . . Y
n−1
and Y
n
. Otherwise, in the case in which the dielectric layer
141
is disposed on the front surface of the common electrode lines X
1
, X
2
, . . . , X
n−1
and X
n
, the phosphor
142
may be the dielectric layer (
141
of FIG.
3
).
The common electrode lines X
1
, X
2
, . . . , X
n−1
and X
n
and the scan electrode lines Y
1
, Y
2
, . . . , Y
n−1
and Y
n
are formed on the rear surface of the front glass substrate
10
in a predetermined pattern, orthogonal to the address electrode lines A
1
, A
2
, A
3
, . . . , A
m−2
, A
m−1
and A
m
. Pixels are defined at the respective points of intersection. The respective common electrode lines X
1
, X
2
, . . . , X
n−1
and X
n
and the respective scan electrode lines Y
1
, Y
2
, . . . Y
n−1
and Y
n
are constituted by indium tin oxide (ITO) electrode lines X
na
and Y
na
shown in FIG.
3
and metal bus electrode lines X
nb
and Y
nb
shown in FIG.
3
. The dielectric layer
11
coats the rear surface of the common electrode lines X
1
, X
21
, . . . , X
n−1
and X
n
and the scan electrode lines Y
1
, Y
2
, . . . Y
n−1
and Y
n
. The magnesium monoxide (MgO) layer
12
for protecting the panel
1
against a strong electrical field coats the rear surface of the dielectric layer
11
. A discharge space
14
is filled with plasma forming gas.
The plasma display panel thus constructed is basically driven such that the reset step, the address step and the sustaining discharge step are sequentially performed on unit subfields. In the reset step, wall charges remaining on the previous subfield are eliminated. In the address step, wall charges are formed in a selected pixel region. In the sustaining discharge step, light is generated at the pixel in which the wall charges are formed in the address step. In other words, if an alternating pulse having a relatively high voltage is applied between the common electrode-lines X
1
, X
2
, . . . , X
n−1
and X
n
and the scan electrode lines Y
1
, Y
2
, . . . Y
n−1
and Y
n
, a surface discharge occurs at the wall-charge formed pixel. Here, a plasma is formed in the discharge space
14
and the phosphor
142
is excited by ultraviolet radiation to generate light.
Here, multiple unit subfields operating based on the above-described driving principle are included in the unit frame, so that desired gray scale display can be achieved with the interval of sustaining discharge periods of the respective subfields.
The conventional driving methods using such driving principles include an address-display-separation driving method and an address-while-display driving method.
According to the address-display separation driving method, an address period and a sustaining discharge period are separated in a unit subfield set for gray-scale display. Accordingly, it is easy to design and modify a driving apparatus and the configuration of the driving apparatus is simplified. However, the sustaining discharge period is made to be relatively shorter, which lower display luminance.
According to the address-while-driving method, an address period is included within a display period of each subfield and the respective subfields start sequentially with a unit time interval for each scan electrode line and overlap with one another. Accordingly, the sustaining discharge period is relatively longer, which increases display luminance. However, it is difficult to design and modify the driving apparatus and the driving apparatus becomes complicated.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a method for driving a plasma display panel by which a driving apparatus can be easily designed and modified, the configuration of the driving apparatus is simplified and display luminance is enhanced.
Accordingly, to achieve the above object, there is provided a driving method of a plasma display panel for performing gray-scale display by a plurality of subfields in each of which an address step, a sustaining discharge step and a reset step are performed. The method includes the step of dividing the unit frame to be displayed into unit drive periods corresponding to the number of gray scales. Each unit drive period is into three periods; a unit address period, a unit sustaining discharge period and a unit reset period. The respective unit address periods are equal to one another, the respective unit sustaining discharge periods are equal to one another and the respective unit reset periods are equal to one another. Each unit address period is divided into the same number of time intervals as there are subfields and the divided time intervals are allocated to the respective subfields, allowing the respective subfields to start sequentially with a time interval corresponding to the unit drive period to then overlap with one another. An address voltage is applied between the scan electrode line and the address electrode line corresponding to the first unit drive period of the subfields during the time interval allocated to each unit address period. A sustaining discharge voltage is applied between the common electrode lines and all the scan electrode lines during all the unit sustaining discharge periods, and a reset voltage is applied between the common electrode lines and the scan electrode lines corresponding to the last unit drive period of the subfields during each unit reset period.
During every unit sustaining discharge period, even if a sustaining discharge voltage is applied between the common electrode lines and scan electrode lines, a sustaining discharge is performed at only the pixels selected in the directly previous address period and having wall charges formed therein.
As described above, according to the driving method of the present invention, the plasma display panel is driven for each unit drive period, and a sustaining discharge voltage is applied between the common electrode lines and scan electrode lines during every unit sustaining discharge period. Accordingly, the design and modification of the driving apparatus is facilitated and the configuration of the driving apparatus is simplified. Also, the respective subfields sequentially start with a time interval corresponding to the unit drive period with respect to each scan electrode line to then overlap with one another. Accordingly, the length of the sustaining discharge period within a unit frame becomes relatively larger, thereby enhancing the display luminance.
REFERENCES:
patent: 6054970 (2000-04-01), Hirakawa et al.
patent: 6072448 (2000-06-01), Kojima et al.
patent: 6292159 (2001-06-01), Someya et al.
patent: 6262699 (2001-07
Eo Yoon-phil
Kang Kyoung-ho
Ryeom Jeong-duk
Leydig , Voit & Mayer, Ltd.
Liang Regina
Samsung SDI & Co., Ltd.
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