Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-04-04
2003-09-30
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S067000
Reexamination Certificate
active
06628250
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for driving a plasma display panel, and more particularly, to a method for driving a three-electrode surface-discharge alternating-current plasma display panel.
2. Description of the Related Art
FIG. 1
shows a structure of a general three-electrode surface-discharge alternating-current plasma display panel,
FIG. 2
shows an electrode line pattern of the panel shown in
FIG. 1
, and
FIG. 3
shows another example of a pixel of the panel shown in FIG.
1
. Referring to the drawings, address electrode lines A
1
, A
2
, A
3
, . . . , A
m−2
, A
m−1
and A
m
, a dielectric layer
11
(and/or
141
of FIG.
3
), scan electrode lines Y
1
, Y
2
, . . . , Y
n−1
and Y
n
, common electrode lines X
1
, X
2
, . . . , X
n−1
and X
n
and a MgO protective film
12
are provided between front and rear glass substrates
10
and
13
of a general surface-discharge plasma display panel
1
.
The address electrode lines A
1
, A
2
, A
3
, . . . , A
m−2
, A
m−1
and A
m
, are arranged on the entire surface of the rear glass substrate
13
in a predetermined pattern. Phosphors (
142
of
FIG. 3
) may coat the entire surface of the scan electrode lines Y
1
, Y
2
, Y
n−1
and Y
n
. Otherwise, the phosphors
142
may coat a dielectric layer
141
in the event the dielectric layer
141
coats the entire surface of the scan electrode lines Y
1
, Y
2
, . . . , Y
n−1
and Y
n
in a predetermined pattern.
The common electrode lines X
1
, X
2
, . . . , X
n−1
and X
n
and the scan electrode lines Y
1
, Y
2
, . . . , Y
n−1
and Y
n
are arranged on the rear surface of the front glass substrate
10
, orthogonal to the address electrode lines A
1
, A
2
, A
3
, . . . , A
m−2
, A
m−1
and A
m
, in a predetermined pattern. The respective intersections define corresponding pixels. The common electrode lines X
1
, X
2
, . . . , X
n−1
and X
n
and the scan electrode lines Y
1
, Y
2
, . . . , Y
n−1
and Y
n
each comprise of indium tin oxide (ITO) electrode lines X
na
and Y
na
, and metal bus electrode lines X
nb
and Y
nb
, as shown in FIG.
3
. The dielectric layer
11
entirely covers the rear surface of the common electrode lines X
1
, X
2
, . . . , X
n−1
and X
n
and the scan electrode lines Y
1
, Y
2
, . . . , Y
n−1
and Y
n
. The MgO protective film
12
for protecting the panel
1
against strong electrical fields entirely coats the rear surface of the dielectric layer
11
. A gas for forming plasma is hermetically sealed in a discharge space.
The driving method generally adopted for the plasma display panel described above is an address/display separation driving method in which a reset step, an address step and a sustain-discharge step are sequentially performed in a unit subfield. In the reset step, wall charges remaining in the previous subfield are erased. In the address step, the wall charges are formed in a selected pixel area. Also, in the sustain-discharge step, light is produced at the pixel at which the wall charges are formed in the address step. In other words, if alternating pulses of a relatively high voltage are applied between the common electrode lines X
1
, X
2
, . . . , X
n−1
and X
n
and the scan electrode lines Y
1
, Y
2
, . . . , Y
n−1
and Y
n
, a surface discharge occurs at the pixel at which the wall charges are formed. Here, a plasma is formed at the gas layer of the discharge space
14
and the phosphors
142
are excited by ultraviolet rays to thus emit light.
Here, several unit subfields basically operating on the principles as described above are contained in a unit frame, thereby achieving a desired gray scale display by sustain-discharge time intervals of the respective subfields.
In the above-described method for driving the plasma display panel
1
, conventionally, a relatively high discharge voltage is applied to all common electrode lines X
1
, X
2
, . . . , X
n−1
and X
n
in the reset step, thereby erasing wall charges formed at the pixels in the previous subfields and generating a uniform space charge. However, according to the conventional driving method, since erasing discharge occurs around all common electrode lines X
1
, X
2
, . . . , X
n−1
and X
n
, the contrast of a screen is deteriorated.
SUMMARY OF THE INVENTION
To solve the above problem, it is an objective of the present invention to provide a method for driving a plasma display panel which can increase the contrast of the plasma display panel.
Accordingly, to achieve the above objective, there is provided a method for driving a plasma display panel having a front substrate and a rear substrate facing and spaced apart from each other, and n common electrode lines, n scan electrode lines and m address electrode lines arranged between the front and rear substrates (m and n are integers of greater than or equal to 2), the common electrode lines and the scan electrode lines being parallel to each other, the address electrode lines being arranged to be orthogonal to the scan electrode lines, to define pixels at the respective intersections, the method including the steps of (1) in order to distribute the n common electrode lines to k common electrode groups (k is an integer of greater than or equal to 2), setting (p+k·j)th common electrode lines to be included in the p-th common electrode group (p is an integer of greater than or equal to 1 and j is an integer of greater than or equal to 0), (2) setting a unit frame to be displayed into k subfields, and (3) applying a relatively high discharge voltage to the electrode lines of the p-th common electrode group in the p-th subfield among the respective subfields, thereby erasing wall charges formed at the pixels and forming uniform space charges.
According to the driving method of the present invention, a relatively high discharge voltage is applied to only electrode lines of the corresponding common electrode group in each subfield. Accordingly, since an erase discharge takes place only around the electrode lines of the corresponding common electrode group, the contrast of a screen can be further enhanced. Also, since the (p+k·j)th common electrode lines are set to be included in the p-th common electrode group, an erase discharge occurs with a constant time interval with respect to all areas in the discharge space. Accordingly, the effect of the erase discharge is maintained and no flicker is generated.
REFERENCES:
patent: 4044349 (1977-08-01), Andoh et al.
patent: 4638218 (1987-01-01), Shinoda et al.
patent: 4737687 (1988-04-01), Shinoda et al.
patent: 5663741 (1997-09-01), Kanazawa
patent: 5854540 (1998-12-01), Matsumoto et al.
patent: 6292160 (2001-09-01), Mikoshiba et al.
patent: 6373452 (2002-04-01), Ishii et al.
Kim sang-chul
Yoo Ji-seung
Hjerpe Richard
Leydig , Voit & Mayer, Ltd.
Nguyen Kevin M.
Samsung SDI & Co., Ltd.
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