Computer graphics processing and selective visual display system – Display driving control circuitry – Waveform generator coupled to display elements
Reexamination Certificate
1998-04-17
2001-06-05
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Waveform generator coupled to display elements
C345S060000, C345S062000, C345S067000, C345S068000, C345S215000, C315S167000, C315S169400
Reexamination Certificate
active
06243084
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for driving a plasma display including cells defined at intersections of a plurality of electrodes.
2. Description of the Background Art
FIG. 11
shows an overview of a configuration of a background-art plasma display such as disclosed in Japanese Patent Application Laid Open Gazette 7-160218. This figure shows a display panel
101
, sustain electrodes X serving as the first electrodes and scan electrodes Y
1
to Yn serving as the second electrodes which are disposed in parallel on a glass substrate serving as the first substrate and address electrodes A
1
to Am serving as the third electrodes arranged on a glass substrate serving as the second substrate opposed to the above-mentioned glass substrate in a direction perpendicular to the sustain electrodes X and the scan electrodes Y
1
to Yn.
The plasma display has n×m pixels, that is i=1 to n and j=1 to m, and a discharge cell is defined at an intersection between a given scan electrode Yi and a given address electrode Aj. The scan electrodes Y
1
to Yn and the address electrodes A
1
to Am are insulated from and independent of one another so as to be independently driven to perform address selection for each of the defined discharge cells to turn on/off.
The sustain electrodes X are paired with the scan electrodes Y
1
to Yn respectively and respective one ends of the sustain electrodes X are connected in common. The first to fourth voltages to be applied to these electrodes as pulses are generated by a power supply circuit
102
and then supplied for the electrodes through a Y common driver
103
, a scan driver
104
, an X common driver
105
and an address driver
106
. The Y common driver
103
, the scan driver
104
, the X common driver
105
and the address driver
106
are controlled by a control signal from a control circuit
107
. The control circuit
107
generates the control signal based on externally-supplied display data DATA, a dot clock CLK, a vertical synchronizing signal VSYNC and a horizontal synchronizing signal HSYNC in synchronization with the display data.
FIG. 12
is a cross-sectional illustration showing a structure of a cell in the plasma display panel. This figure shows the sustain electrode X and the scan electrode Yi both of which are formed on a glass substrate
108
extending in a direction perpendicular to this paper, a dielectric layer
109
for holding wall charges formed on the sustain electrode X and the scan electrode Yi, a protective layer
110
formed on a surface of the dielectric layer
109
, the address electrode Aj formed on a glass substrate
111
opposed to the glass substrate
108
, extending in a side-to-side direction of this paper, a phosphor
112
formed on the address electrode Aj, a barrier rib
113
formed on a pixel boundary and a discharge space
114
between the protective layer
110
and the phosphor
112
, being filled with, for example, Penning mixed gas of Ne and Xe.
Now, an operation will be discussed.
FIG. 13
is an illustration of applied voltage waveforms for showing a background-art method for driving a plasma display, with a resetting step, a writing step and a discharge sustaining step in time series. In this figure, prior to the writing step, a priming pulse
121
is applied as a pulse of the first voltage between the sustain electrode X and the scan electrode Yi in the resetting step, to cause a discharge between the sustain electrode X and the scan electrode Yi, producing space charges in the discharge space
114
, and to cause a self-erase discharge on a fall of the priming pulse
121
, bringing a state of charges in the cell into a charge-erased state (where accumulated charges in the dielectric layer
109
on the sustain electrode X and the scan electrode Yi become zero). Subsequently, in the writing step, a scan pulse
122
is applied to the scan electrodes Y
1
to Yn in sequence and an address pulse is applied to the address electrodes A
1
to Am in accordance with the display data, to generate the second voltage across the address electrodes A
1
to Am and the scan electrodes Y
1
to Yn, causing a writing discharge. After that, in the discharge sustaining step, a sustain pulse is applied alternately to the sustain electrode X and the scan electrode Yi as the fourth voltage, to sustain the discharge.
The first voltage refers to a potential difference across the sustain electrode X and the scan electrode Yi. In
FIG. 13
, assuming that the potential of the scan electrode Yi is zero, a pulse of potential Vp is applied to the sustain electrode X and therefore Vp is the first voltage. Alternatively, for example, a pulse of potential Vp&agr; and a pulse of negative potential Vp&bgr; (where the first voltage=Vp&agr;−Vp&bgr;) may be applied to the sustain electrode X and the scan electrode Yi, respectively, as discussed later.
Similarly, the second voltage refers to a potential difference across the address electrode Aj and the scan electrode Yi (in
FIG. 13
, Va−Vsp is the second voltage, and since Vsp is a negative potential, the expression, |Va|+|Vsp| is the second voltage, may be made). The fourth voltage refers to a potential difference between the sustain electrode X and the scan electrode Yi (in
FIG. 13
, Vs is the fourth voltage). Thus, a display operation is achieved through repeating the resetting step, the writing step and the discharge sustaining step in sequence.
Next, with reference to FIGS.
14
(
a
0
) to
14
(
f
0
), discussion will be made on state changes inside a cell in the resetting step. FIGS.
14
(
a
0
) to
14
(
f
0
) correspond to time periods (a) to (f) of
FIG. 13
, respectively. After the end of the preceding driving cycle, in respective portions corresponding to the sustain electrode X and the scan electrode Yi which are adjacent to each other, a certain amount of wall charges of reverse polarities are accumulated (FIG.
14
(
a
0
)). In this state, when the priming pulse
121
is applied across the sustain electrode X and the scan electrode Yi, a discharge occurs across the sustain electrode X and the scan electrode Yi (FIG.
14
(
b
0
)). Electrons and positive ions generated by the discharge are attracted towards the reversely-polarized sustain electrode X and scan electrode Yi respectively and accumulated on a surface of the dielectric layer
109
to act as respective wall charges on the sustain electrode X and the scan electrode Yi. Since these wall charges reduce the electric field strength in the discharge space, the discharge immediately converges to a termination (FIG.
14
(
c
0
)).
When the application of the priming pulse
121
to the sustain electrode X and the scan electrode Yi is stopped, a discharge occurs across the sustain electrode X and the scan electrode Yi by the wall charges (FIG.
14
(
d
0
)). Then, the positive ions and the electrons recombine together, to reduce the wall charges (FIG.
14
(
e
0
)). At this time, the wall charges ideally become zero, but in some cases, some of the wall charges actually remain as residual wall charges (FIG.
14
(
f
0
)).
In the resetting step, the priming pulse
121
(full write pulse) applied across the sustain electrode X and the scan electrode Yi performs the following functions;
a. to once forcefully cause a discharge, regardless of the previous display state, resetting the state of the charges into a relatively uniform state,
b. to generate space charges for easy subsequent discharges, and
c. to perform an erase operation (to return all the discharge cells into an erased state, that is, a state of no accumulated charge).
With the above configuration of the background-art plasma display, all the wall charges are not necessarily erased by the self-erase discharge and some residual wall charges are left in some cases. Until now, it has been believed that it is no problem if the residual wall charges cause no false discharge in a cell of no writing, in other words, cause no erase failure in terms of quantity.
Kovalick Vincent E.
Mitsubishi Denki & Kabushiki Kaisha
Shalwala Bipin
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