Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-05-17
2003-04-08
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185130
Reexamination Certificate
active
06545915
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for driving a nonvolatile semiconductor memory device such as a flash memory that is electrically rewritable.
The flash memory enables high degree of integration as a nonvolatile semiconductor memory device that is capable of data programing and erasing. Thus, many memory cell structures and driving methods of a flash memory have been developed. One of many proposals regarding the memory cell structures is found in Japanese Patent Laid-Open Publication No. JP-A 11-31396. It discloses a memory cell structure that involves injection and pulling-out of electrons (i.e., programing and erasing operations) through a tunnel oxide between a channel region and a floating gate and enables high speed access and high degree of integration, and implements a good endurance property (resistance to deterioration of a memory cell due to programing and erasing operations).
FIG. 3
shows a schematic block diagram of an NOR flash memory for a typical example of such a nonvolatile semiconductor memory device. A memory cell used in the flash memory is a floating-gate MOS (metal oxide semiconductor) field-effect transistor that has a structure as shown in FIG.
4
. More particularly, the memory cell is composed of a source
2
and a drain
3
formed on a surface of a semiconductor substrate
1
, a channel region formed between the source
2
and the drain
3
, and a floating gate
5
and a control gate
7
formed on the channel region. Further, an interlayer insulating film
6
is provided between the control gate
7
and the floating gate
5
, and a tunnel oxide
4
is provided between the floating gate
5
and the channel region.
As shown in
FIG. 3
, the flash memory is composed of a high voltage pump (high voltage generating circuit)
11
, a negative voltage pump (negative voltage generating circuit)
12
, regulator circuits
13
-
15
, a memory cell array
16
, a column decoder
17
, a row decoder
18
, an erasing circuit
19
, a drain select gate (sg) circuit
20
, and a source select gate (sg) circuit
21
.
The high voltage pump
11
outputs a positive voltage Vpp−Veg raised based on a voltage Vcc. On the other hand, the negative voltage pump
12
outputs a negative voltage Vneg raised based on the voltage Vcc. Consequently, the regulator circuit
13
outputs a voltage Vds based on the positive voltage Vpp from the high voltage pump
11
, the regulator circuit
14
outputs a voltage Vinh based on the positive voltage Vpp, and the regulator circuit
15
outputs a voltage Vpd based on the positive voltage Vpp.
The memory cell array
16
is made up of a plurality of memory cells disposed in a matrix configuration though only one memory cell is shown in FIG.
3
. The column decoder
17
selects a bit line of the memory cell array
16
based on the voltage Vds from the regulator circuit
13
and the voltage Vinh from the regulator circuit
14
. The row decoder
18
selects a word line of the memory cell array
16
based on the positive voltage Vpp from the high voltage pump
11
and the negative voltage Vneg from the negative voltage pump
12
. The erasing circuit
19
performs erase control of memory cells based on the voltage Vds from the regulator circuit
13
.
The drain sg circuit
20
outputs a signal to a drain select gate signal line DSG based on the positive voltage Vpp from the high voltage pump
11
and the voltage Vpd from the regulator circuit
15
. The source sg circuit
21
outputs a signal to a source select gate signal line SSG based on the positive voltage Vpp from the high voltage pump
11
.
FIG. 5
is a circuit diagram showing a specific structure of the regulator circuits
13
,
14
, and
15
. The regulator circuits
13
,
14
, and
15
are composed of an inverting amplifier OP, a transistor Q
1
, a resistance R
1
and a resistance R
2
.
A reference voltage is inputted to a non inverting input terminal of the inverting amplifier OP. An output terminal of the inverting amplifier OP is connected to a gate of the transistor Q
1
. The voltage Vpp is inputted to a drain of the transistor Q
1
. A source of the transistor Q
1
is connected to one end of the resistance R
1
. The other end of the resistance R
1
is connected to an inverting input terminal of the inverting amplifier OP and to one end of the resistance R
2
. The other end of the resistance R
2
is connected to a ground.
By setting appropriate values of resistance for the resistance R
1
and the resistance R
2
, there are outputted from the source of the transistor Q
1
, a voltage Vds in the case of the regulator circuit
13
, a voltage Vinh in the case of the regulator circuit
14
, and a voltage Vpd in the case of regulator circuit
15
.
In the above-structured flash memory, a voltage necessary for programing and erasing operations is obtained from the high voltage pump
11
, the negative voltage pump
12
, and the regulator circuits
13
,
14
, and
15
. More particularly, the high voltage pump
11
generates a voltage Vpp in programing operation, a voltage Vbias (approx. 5V) in reading operation, and a voltage Veg in erasing operation. The negative voltage pump
12
does not operate in programing operation where negative voltage is not necessary, but generates a voltage Vneg in erasing operation.
Table 1 shows voltages applied to each electrode and a semiconductor substrate of a memory cell in programing (writing), erasing and reading operations.
TABLE 1
Gate
Drain
Source
Substrate
Programing
Vpp
Vss/Vinh
Vss/Vinh
Vss
Erasing
Vneg
Vds(F)
Vds(F)
Vds
Reading
Vcc
Vbias
Vss
Vss
Vss/Vinh herein indicates that a voltage Vss is applied in programing of data “0”, and a voltage Vinh is applied in programing of data “1”. Vds(F) indicates that a voltage Vds is applied or that a floating state (F) is set.
FIG. 6
shows a state of writing to a memory cell of a flash memory having the structure shown in FIG.
4
. In the application voltage conditions of programing operation, as shown in Table 1, the voltage Vpp (for example +15V: a control gate voltage in programing operation) is applied to the control gate
7
, and the voltage Vss (for example 0V: reference voltage) is applied to the source
2
, the drain
3
and the semiconductor substrate
1
. This induces electrons in a channel region c, which in turn generates high electric fields between the floating gate
5
and the channel region c. As a result, electrons are injected into the floating gate
5
through the tunnel oxide
4
(see FIG.
4
).
FIG. 7
shows an erase state. In erasing operation, the voltage Vneg (for example −10V: a control gate negative voltage in erasing operation) is applied to the control gate
7
. The source
2
and the drain
3
are set to be in a floating state or applied by the voltage Vds (for example 0V to +6V). The voltage Vds is applied to the semiconductor substrate
1
. Those conditions pull electrons from the floating gate
5
to the channel region c through the tunnel oxide
4
.
FIG. 8
shows a distribution of threshold voltages in the erasing and writing states of a memory cell. The horizontal axis shows threshold voltages Vth of the memory cells, while the vertical axis shows number of the memory cells having respective threshold voltages Vth.
FIG. 9
shows a detailed structure of the memory cell array
16
shown in FIG.
3
. In
FIG. 9
, local bit lines LBL
0
, LBL
1
, . . . , LBLm are connected in common to drains of memory cells M
00
to Mn
0
, M
01
to Mn
1
, . . . , M
0
m to Mnm existing in the same rows, respectively. Also, the local bit lines LBL
0
, LBL
1
, . . . , LBLm are connected to main bit lines BL
0
to BLm respectively, through select transistors ST
10
, ST
11
, . . . , ST
1
m as the first MOS transistor. Local source lines LSL
0
, LSL
1
, . . . , LSLm are connected in common to sources of the memory cells M
00
to Mn
0
, M
01
to Mn
1
, . . . , M
0
m to Mnm existing in the same rows, respectively. Also, the local source lines LSL
0
, LSL
1
, . . . , LSLm are connected to a common source line CSL respectively, through select transistors ST
Ohtani Shigehiro
Yamano Kaname
Hoang Huan
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
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