Method for driving bit line selecting signals

Details Method for driving bit line selecting signals Method for driving bit line selecting signals

1995-01-31

1996-03-12

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365203, 36518911, 36518908, 36523003, G11C 800

Patent

active

054992184

ABSTRACT:
A method for driving bit line selecting signals is disclosed, in which the DRAM cell includes a plurality of memory cell arrays, sense amplifiers, bit lines, bit line equalizer sections, bit line selecting sections, data input/output sections, and bit line selection signal generating sections. According to the present invention, the bit line selecting signals operate in such a manner that: during a bit line selection, a bit line selecting signal for connecting one pair of bit lines among the n pairs of bit lines to the sense amplifier is made to have a voltage level capable of connecting the bit lines to the sense amplifier by the help of the bit line selecting section without a voltage loss; the other bit line selecting signals corresponding to the non-selected remaining bit lines are given a voltage incapable of connecting the bit lines the sense amplifier by the bit line selecting section; thereafter, during the pre-charging for a bit line equalization, the bit line selecting signal corresponding to the bit line which was selected just before is given a voltage capable of connecting the bit lines to the sense amplifier by the help of the bit line selecting section; and the bit line selecting signals which do not correspond to the bit line selected just before are maintained without a voltage shifting.

REFERENCES:
patent: 5280448 (1994-01-01), Watanabe
patent: 5343432 (1994-08-01), Matsuo et al.
patent: 5357472 (1994-10-01), Shirota
patent: 5377151 (1994-12-01), Komuro
"Twisted Bit-Line Architectures for Multi-Megabit DRAM's", Hideto Hidaka et al., IEEE Journal of Solid State Circuits, vol. 24, No. 1, Feb. 1989.

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