Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-02-22
2002-05-21
Lao, Lun-Yi (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S094000, C349S047000
Reexamination Certificate
active
06392623
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention:
The present invention relates to a method for driving an active matrix substrate for use in a liquid crystal display device. The present invention also relates to a liquid crystal display device to which the method is applied.
2. Description of the Related Art:
An active matrix type liquid crystal display device typically includes two substrates. On one of the two substrates a counter electrode is provided, while on the other substrate, a plurality of pixel electrodes are arranged. These substrates are attached together in such a way as to face each other while sandwiching a liquid crystal layer. The liquid crystal display device selectively drives the pixel electrodes for displaying.
The substrate on which the pixel electrodes are provided is here referred to as an active matrix substrate.
FIG. 7
shows a plan view of the active matrix substrate. In
FIG. 7
, a plurality of signal lines
101
intersect a plurality of scanning lines
102
(here they are orthogonally crossed). A single switching element
103
is provided at each intersection. The switching element
103
is a thin film transistor (TFT). A scanning line
102
is connected to the gate of each switching element
103
, and a signal line
101
is connected to the source of each switching element
103
. A pixel capacitor
104
and an storage capacitor
105
are provided for each switching element
103
, both being connected to the drain of the switching element
103
. A common signal line
106
is provided parallel to each scanning line
102
. A terminal
101
a
is provided at an end of each signal line
101
and a terminal
102
a
is provided at an end of each scanning line
102
.
A pixel capacitor
104
is formed between a pixel electrode provided on the active matrix substrate and the counter electrode provided on the other substrate facing the active matrix substrate. An storage capacitor
105
is formed between each pixel electrode and a common signal line
106
.
In such an active matrix substrate, the scanning lines
102
are sequentially scanned. The switching elements
103
connected to each scanning line
102
are switched ON when it is being scanned. A signal voltage is applied via a signal line
101
to the ON-switched switching element
103
. The signal voltage is in turn applied via the ON-switched switching element
103
to a pixel electrode. All the scanning lines
102
are scanned while the corresponding signal voltage is applied to each of the pixel electrodes, resulting in displaying an image.
FIG. 8
is a cross-sectional, partially enlarged, view of the active matrix substrate. In
FIG. 8
, a gate electrode
103
a
of the switching element
103
(TFT) and the common signal line
106
are formed on a transparent insulative substrate
111
. A gate insulator film
112
is provided to cover the gate electrode
103
a
and the common signal line
106
as well as the substrate
111
. A semiconductor layer
113
, a source electrode
114
, a drain electrode
115
, a signal line
101
, and a draw line
107
(conductive layer) are successively formed on the gate insulator film
112
. This multi-layer structure is covered with an interlayer insulator film
117
. Subsequently, a contact hole
117
a
is formed in the interlayer insulator film
117
, and a pixel electrode
118
is then provided on the interlayer insulator film
117
and the contact hole
117
a
in such a way as to contact the draw line
107
.
FIG. 9
roughly shows a fabrication process of the above-described active matrix substrate. Firstly, a semiconductor layer is formed on the transparent insulative substrate
111
, and is then patterned to form the scanning line
102
(see FIG.
1
), the gate electrode
103
a
, the common signal line
106
(step
201
). An insulator film, an amorphous-silicon layer and an n
+
-Si layer are successively disposed to cover the gate electrode
103
a
and the common signal line
106
as well as the substrate
111
. The amorphous-silicon layer and the n
+
-Si layer are subjected to patterning to form the semiconductor layer
113
, the source electrode
114
and the drain electrode
115
(step
202
). The insulator film is then subjected to patterning to form the gate insulator film
112
(step
203
). This patterning results in a contact region
112
a
formed in the gate insulator film
112
which is used to connect the terminal
101
a
of the signal line
101
and the terminal
102
a
of the scanning line
102
(shown in
FIG. 7
) to the outside. The resultant multi-layer structure is then covered with a conductive layer. The conductive layer is subjected to patterning to form the signal line
101
, the draw line
107
. This patterning removes a portion of the n
+
-Si layer between the source electrode
114
and the drain electrode
115
, so that both the electrodes are separated from each other (step
204
). The interlayer insulator film
117
with the contact hole
117
a
is disposed on the resulting multi-layer structure (step
205
). Finally, a conductive layer is formed on the interlayer insulator film
117
and is then subjected to patterning, resulting in the pixel electrode
118
(step
206
).
To reduce the number of photomasks used in the above-described fabrication process, step
202
and step
203
may be integrated into a single step, i.e., the source electrode
114
, the drain electrode
115
, and the gate insulator film
112
are simultaneously subjected to patterning.
When step
202
and step
203
are performed by one step, the semiconductor layer is inevitably disposed on the gate insulator film
112
, so that the gate insulator film
112
, the semiconductor layer, and the draw line
107
are successively formed on the common signal line
106
. This multi-layer structure is a metal-insulator-semiconductor (MIS) structure, which creates a storage capacitor between the common signal line
106
and the pixel electrode
118
. The MIS structure has capacitance-voltage characteristics in which the capacitance of the MIS structure varies depending on voltage applied to the pixel electrode
118
. The change in the capacitance affects the voltage applied to the pixel electrode
118
due to the relationship Q=CV, causing the gray level of the pixel to deviate from an intended level.
FIG. 10
is a graph showing a signal voltage Vs for a single signal line
101
, a scanning voltage Vg for a single scanning line
102
, a voltage Vp for a single pixel electrode
118
and a voltage Vc for the common signal line
106
. When the scanning voltage Vg is at a high level, the pixel electrode
118
is connected via the switching element
103
to the signal line
101
. In this case, the signal voltage Vs is applied to the pixel electrode
118
the voltage of which is in turn set to Vp. The voltage Vp of the pixel electrode
118
is slightly lowered as compared with the signal voltage Vs due to the TFT of the switching element
103
. The potential of the common signal line
106
is set to the same level as that of the counter electrode potential. The voltage Vc of the common signal line
106
agrees with the average value of the voltage Vp of the pixel electrode
118
.
Here, the amplitude of the signal voltage Vs has a range having its center around 0 V. The voltage between the common signal line
106
and the pixel electrode
108
varies, which leads to variation of the capacitance of the MIS structure and thus the capacitance of the storage capacitor between the common signal line
106
and the pixel electrode
118
. For this reason, the voltage Vp of the pixel electrode
118
deviates from an intended value, thereby causing the gray scale of the pixel to be unstable.
To prevent the variation of the capacitance of the storage capacitor caused by the voltage applied to the pixel electrode, Japanese Patent Publication No. 2856789 discloses a method for driving a display device in which a voltage is applied to the common signal line in such a way as to hold the capacitor of the MIS structure, which is included in the storage capacitor structure,
Conlin David G.
Dike, Bronstein Roberts & Cushman, Intellectual Property Group o
Lao Lun-Yi
Manus Peter J.
Sharp Kabushiki Kaisha
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