Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Utilizing three or more electrode solid-state device
Reexamination Certificate
2002-09-19
2004-11-02
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Utilizing three or more electrode solid-state device
Reexamination Certificate
active
06812772
ABSTRACT:
FIELD OF THE INVENTION
The invention concerns the field of high-power electronics.
It relates to a method for driving a power semiconductor element, the power semiconductor element being an integrated gate dual transistor (GDT) having two controllable gates, a first gate being provided on the cathode side and being driven via a low-inductance first gate terminal with a first gate current, and a second gate being provided on the anode side and being driven via a low-inductance second gate terminal with a second gate current.
It further relates to a circuit arrangement for carrying out this method.
BACKGROUND OF THE INVENTION
In the field of power electronics, the search for the optimal turn-off semiconductor element has produced various fast, powerful semiconductor elements. To achieve even larger switched powers it is necessary to reduce losses for the semiconductor elements that are becoming ever smaller. Both dynamic switching losses and steady-state conducting or blocking losses lead to high temperatures and limit switching power and frequency.
The Gate Turn-Off thyristor (GTO) is a turn-off semiconductor element—known for a number of years—with a characteristic recovery time and a turn-off gain of greater than 1. For turn-off, a turn-off command in the form of a positive current is applied to a cathodal gate of the GTO. The gate current is controlled by a gate driver. The recovery or reaction time between the turn-off command and the actual turn-off process is a multiple of the actual switching duration and depends both on the present operating state, in particular on the current intensity to be switched, and on the gate driver. This makes, in particular, snubberless turn-off of GTOs impossible, and connection in series and connection in parallel very complicated.
The dual gate GTO, as is described in Tsuneo Ogura et al., “
High-Frequency
6000
V Double Gate GTOs”
1993
, IEEE Transactions on Electron Devices
, Vol 40. No. 3, has an additional gate on the anode side in comparison with the normal GTO, which results in the possibility of initiating the turn-off operation by means of a respective gate driver on both sides of the element. The advantage of the significantly reduced turn-off losses is opposed here by the significantly more complicated gate driver. This is because if the GTO already has considerable reaction times dependent on the operating state, it is not surprising that the dual gate GTO reacts in an even more complex manner. On the cathode side and on the anode side, significantly different recovery times result which are in turn dependent on the respective operating state and also on the two gate drivers. Thus, the switching of a dual gate GTO is not just necessarily associated with delays, it also requires an extremely precise timing, dependent on the operating state, between the two gate drivers. The time pattern for the driving of a dual gate GTO is thus much more complex than for a normal GTO. For this reason, the dual gate GTO has not gained acceptance in practice, even though it has been known for more than 10 years and could potentially have considerable advantages.
The Integrated Gate-Commutated Thyrister (IGCT), as is described in S. Eicher et al., “
The
10
kV IGCT—A New Device for Medium Voltage Drives”, IEEE
-
IAS
2000, is a further turn-off semiconductor element with a turn-off gain of less than or equal to 1 and a very short reaction time. The IGCT is a “hard” driven trench GTO. The concept of “hard” driving is based on a new type of gate driver and a very low-inductance gate connection to the active part. This results in a series of significant advantages, in particular an extremely short switching delay time, the possibility of the snubberless circuit and also the improved possibility of the series circuit. Compared with the GTO, it is additionally possible to increase the switching power, generally up to a fixed specific switching power per area. As a result, the complicated scaling rules of the GTO are also obviated. Moreover, as a result of homogeneously obtained specific switching power per area, the IGCT avoids local overheating and thus a thermal instability. The terms and concepts “hard-driven” and “hard-control” were disclosed, for example, in an article entitled “
IGCT—A New Emerging Technology For High
-
Power, Low-Cost Inverters
”, authored by Peter K. Steimer, et al, and published in ABB Review, pages 34-42, May 1998.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a method for driving an integrated gate dual transistor (IGDT) which is tailored to the properties of the IGDT and thus allows optimal operation of the IGDT, and also of providing a circuit arrangement for carrying out this method.
The object is achieved by means of a method having the features of patent claim
1
and a circuit arrangement having the features of patent claims
7
or
8
.
Driven according to the method according to the invention, the strengths of the IGDT can be utilized optimally.
With hard driving of in each case one or both gates, it is possible to minimize switching losses as a result of fast switching and as a result of reduction of the tail current.
In particular in the case of the turn-off operation of the IGDT, the hard driving of the anodal gate leads to a considerable reduction of the turn-off losses in comparison with the conventional IGCT, it being possible to use, in particular, other settings of the lifetime of the charge carriers (lifetime control techniques).
The optimization of lifetime control combined with the high-gain anode structure enables the on-state losses of the IGDT to be reduced by 20 to 50% compared with conventional IGCTs.
Through simultaneous reduction of switching and on-state losses, it is possible to design the IGDT for higher voltages (10 kV) than the conventional IGCT (6 kV).
By limiting the rate of rise of the voltage across the IGDT via the two gates in the switch-off operation of the IGDT, and/or by controlling the reverse current between anode and cathode via the two gates in the switched-off state of the IGDT, the use of the IGDT in series circuits is facilitated.
Limiting the rate of rise of the voltage across the IGDT prevents voltages from building up at different speeds in a series circuit of IGDTs, and thus unequal loads from overheating or even destroying the individual IGDTs. Likewise in the switched-off state, in which unequal reverse currents would result in different voltage drops across individual IGDTs, which would in turn lead to enormous loads through to the destruction of individual IGDTs. Reverse currents can be reduced by the anodal gate of the IGDT by up to 50% compared with conventional IGCTs. The method according to the invention thus enables turn-off power semiconductors to be connected in series, without parallel-connected resistors.
In addition, the use of the IGDT in parallel circuits is made possible by the fact that, in the switch-on operation of the IGDT, the rate of rise of the anode current is limited via the two gates.
By limiting the reverse current between anode and cathode through both gates in the switched-off state, the IGDT can be operated with a higher depletion layer temperature, thereby enlarging the safe operating area (SOA) of the IGDT.
The improved thermal budget which can be complied with by virtue of the abovementioned advantages allows the IGDT to operate with up to 100% higher switching frequencies in comparison with conventional IGCTs.
In contrast to conventional dual gate GTOs, with the IGDT the gate current of one of the gates can be controlled during the turn-off. It is thus possible to prevent dangerous voltage spikes as occur, for instance, when currents suddenly cut off (snap off) in diodes or dual gate semiconductors.
Further advantageous embodiments emerge from the totality of the dependent claims.
REFERENCES:
patent: 4129809 (1978-12-01), Rosa
patent: 4208711 (1980-06-01), Baker
patent: 5144401 (1992-09-01), Ogura et al.
patent: 5150271 (1992-09-01), Unterweger et al.
patent: 6188267 (2001-02-01), Sanchez et al.
S. Eicher et al
Apeldoorn Oscar
Carroll Eric
Streit Peter
Weber Andre
ABB (Schweiz) AG
Burns Doane Swecker & Mathis L.L.P.
Wells Kenneth B.
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