Method for driving a plasma display panel

Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix

Reexamination Certificate

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Details

C348S625000, C348S537000, C345S058000, C345S208000

Reexamination Certificate

active

06392616

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method for driving a plasma display panel (hereinafter, simply referred to as PDP) of a matrix display scheme.
2. Description of the Related Art
In recent years, in association with the enlargement of a display apparatus, a thin type display apparatus has been requested and various thin type display apparatuses have been put into practical use. An AC (alternate current discharge) type PDP is highlighted as one type of the thin display apparatuses.
The PDP has a plurality of column electrodes (address electrodes) and a plurality of row electrodes arranged so as to cross the column electrodes. Each of the row electrode pairs and the column electrodes are covered with a dielectric material layer against a discharge space and have a structure such that a discharge cell corresponding to one pixel is formed at a cross point of the row electrode pair and the column electrode. Since the PDP performs a light emission display by using a discharge phenomenon, each of the discharge cells has only two states: namely, a state where it emits the light and a state where it does not emit the light. A sub-field method is, therefore, used to realize a halftone luminance display corresponding to an input video signal by the PDP. According to the sub-field method, a display period of one field is divided into N sub-fields, the number of light emission times corresponding to a weight of a bit digit of pixel data (N bits) according to the input video signal is allocated to each sub-field, and the light emission driving is executed.
When a jitter occurs in a vertical sync signal in the input video signal, however, there is a case where a display period of one field becomes short. In this instance, all of the N sub-fields cannot be executed within the short 1-field display period. When the video signal in which the jitter occurred in the vertical sync signal is supplied, therefore, a desired gradation luminance cannot be obtained and there is a problem of deterioration of a display image quality.
OBJECTS AND SUMMARY OF THE INVENTION
The invention is made to solve the problems and it is an object of the invention to provide a method for driving a plasma display panel in which even if a video signal having a jitter is supplied, a preferable image display is performed.
According to the invention, there is provided a method for driving a plasma display panel having discharge cells each corresponding to one pixel formed at each of intersecting points between a plurality of row electrodes arranged at respective scanning lines and a plurality of column electrodes intersecting said row electrodes, comprising the steps of: executing, in each of a plurality of sub-fields forming a display period of one field of an input video signal, a pixel data writing step and a light emission sustaining step, said pixel data writing step being to set each of said discharge cells to one of a light emitting cell and a non-light emitting cell in accordance with a pixel data based on said input video signal, said light emission sustaining step being to allow only said light emitting cells to perform a light emission by a number of times corresponding to a weight of said sub-field, in which at least one of an execution time of said pixel data writing step in each of said sub-fields, an execution time of said light emission sustaining step in each of said sub-fields, and the number of sub-fields within said display period of one field is adjusted in accordance with a jitter of a vertical sync signal in said input video signal.


REFERENCES:
patent: 4129748 (1978-12-01), Saylor
patent: 5003228 (1991-03-01), Hada et al.
patent: 5926174 (1999-07-01), Shibamiya et al.
patent: 6097444 (2000-08-01), Nakano

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