Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-06-05
2003-07-15
Saras, Steven (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S061000
Reexamination Certificate
active
06593903
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for driving a plasma display panel.
2. Description of the Related Background Art
Recently, in line with the increase in the screen size of display apparatuses, the need of thin-shape display apparatuses is increasing, and various kinds of thin display devices have been put into practical use. Much attention is now being paid to an alternate discharge type of plasma display panel as one such thin display device.
FIG. 1
is a schematic configuration of a plasma display apparatus comprising such a plasma display panel and a driver to drive this display panel.
In
FIG. 1
, the plasma display panel PDP
10
comprises m column electrodes D
1-D
m
, and n row electrodes X
1-X
n
and n row electrodes Y
1-Y
n
which intersect each of the column electrodes. A pair of X
i
(1≦i≦n) and Y
i
(1≦i≦n) of the row electrodes X
i-X
n
and Y
i-Y
n
form the 1st to n-th display lines of the PDP
10
. A discharge space containing discharge gas is formed between the column electrode D and the row electrodes X and Y. The intersection of each row electrode and each column electrode with the discharge space in between forms a discharge cell responsible for a picture element.
Each discharge cell emits light by the discharge effect, so each cell can take only two states, namely, a “light emitting” state and a “non-light emitting” state. That is, each discharge cell can show only two gradations, namely, a minimum brightness (non-light emitting state) and a maximum brightness (light emitting state).
Therefore, the driver
100
performs gradation drive by using the subfield method in order to display half-tone brightness corresponding to a video signal supplied to the PDP
10
.
In the subfield method, the input video signal is converted into, for example, 4-bit picture element data corresponding to each picture element. In this case, as is shown in
FIG. 2
, one field is formed of four subfields SF
1
-SF
4
, corresponding to each of the four bits.
FIG. 3
shows various kinds of driving pulses by the driver
100
to be supplied to the row electrodes and the column electrodes of the PDP
10
in one subfield and such pulse supply timing.
In the first place, the driver
100
first supplies positive reset pulses RP
X
to the row electrodes X
1-X
n
, and negative reset pulses RP
Y
to the row electrodes Y
1-Y
n
during a simultaneous reset process Rc. In response to the supply of these reset pulses RP
X
and RP
Y
, all the discharge cells of the PDP
10
are reset and discharged and a predetermined wall charge is uniformly formed in each discharge cell. Immediately after, the driver
100
supplies erasing pulses EP to the row electrodes X
1-X
n
of the PDP
10
at the same time. Because of the supply of said erasing pulses, erasing discharge is performed in each discharge cell and the above-mentioned wall charge disappears. Therefore, all the discharge cells in the PDP
10
are initialized to the “non-light emitting cell” state.
Next, during the picture element data write process Wc, the driver
100
separates each bit of the above-mentioned 4-bit picture element data, matching said bit to the subfields SF
1
-SF
4
, and generates picture element data pulses having a pulse voltage corresponding to the logical level of said bit. For example, during the picture element data write process Wc for the subfield SF
1
, the driver
100
generates picture element data pulses having a pulse voltage corresponding to the logical level of the first bit of said picture element data. In this case, the driver
100
generates picture element data pulses of high voltage when the logical level of the first bit is “1” and it generates picture element data pulses of low voltage (0 volt) when said logical level is “0”. In addition, the driver
100
supplies said picture element data pulses to the column electrodes D
1-D
m
sequentially as picture element data pulse groups DP
1-DP
n
for one display line corresponding to one of the 1st to n-th display lines as is shown in FIG.
3
. In addition, the driver
100
generates negative scanning pulses SP as shown in
FIG. 3
in synchronization with the supply timing of each picture element data pulse group DP, and supplies said scanning pulses to the row electrodes Y
1
-Y
n
sequentially. In this case, only a discharge cell at the intersection of a display line to which said scanning pulses SP were supplied and a “column” to which picture element data pulses of high voltage were supplied discharges (selective erasing discharge). After the completion of said selective write discharge, a wall charge is formed in the discharge cell. Thereby, a discharge cell which was initialized to the “non-light emitting cell” state during the above-mentioned simultaneous reset process Rc is set to the “light emitting cell” state. On the other hand, a discharge cell to which the scanning pulses SP were supplied and at the same time low voltage picture element data pulses were also supplied does not perform the above-mentioned selective write discharge. Thus, this discharge cell is sustained at the state initialized during said simultaneous reset process Rc, namely, at the “non-light emitting cell” state. That is, by the execution of the picture element data write process Wc, each discharge cell in the PDP
10
is set to the “light emitting cell” state or the “non-light emitting cell” state according to the input video signal.
Next, during a light emission sustaining process IC, the driver
100
supplies positive sustaining pulses IP
X
and positive light emission sustaining pulses IP
Y
as shown in
FIG. 3
to the row electrodes X
1
-X
n
and the row electrodes Y
1
-Y
n
alternately and repeatedly. The supply frequency (or the supply period) of these sustaining pulses IP
X
and IP
Y
in one subfield is set according to the weight of each subfield as is shown in FIG.
2
. In this case, only a discharge cell containing a wall charge, namely, only “light emitting cells” perform sustaining discharge each time these sustaining pulses IP
X
and IP
Y
are supplied to such cells. That is, only discharge cells set to the “light emitting cell” state during said picture element data write process Wc emit light by sustaining discharge by a frequency set according to the weight of each subfield as is shown in FIG.
2
.
The driver
100
performs the above-mentioned operation for each subfield. In this case, the half-tone brightness corresponding to the video signal is expressed according to the sum (in one field) of the frequency of said light sustaining discharges in each subfield.
The number of the gradations of brightness which can be expressed by said subfield method increases in proportion to the number of divided subfields. Because the display period of one field is predetermined, it is necessary to narrow the pulse width of the various kinds of driving pulses as is shown in
FIG. 3
in order to increase the number of the subfields. However, an erroneous discharge may take place by narrowing the pulse width of the driving pulses if the number of charged particles remaining in a discharge cell is small. Therefore, a problem was that high image quality cannot always be obtained.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a solution to these problems. The present invention provides a method for driving a plasma display panel capable of displaying a high-quality image.
A method for driving a plasma display panel according to the present invention is a method for driving the gradations of a plasma display panel in which a discharge cell responsible for a picture element is formed at each intersection between each row electrode corresponding to each display line and each column electrode intersected with said row electrode by using each field of an input video signal comprising a plurality of subfields characterized in that: in each of said subfields, a first picture element data write process is executed in response to picture element data corresponding to said input video signal, for
Nakamura Hideto
Shiozaki Yuya
Tokunaga Tsutomu
Anyaso Uchendu O.
Pioneer Corporation
Saras Steven
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