Method for driving a non-volatile semiconductor memory

Details Method for driving a non-volatile semiconductor memory Method for driving a non-volatile semiconductor memory

1996-07-19

1998-02-03

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518508, G11C 1604

Patent

active

057151962

ABSTRACT:
An array of non-volatile memory cells arranged in rows and columns is provided. Each memory cell is composed of a transistor made up of a gate, a source, and drain and a capacitance section. Each memory cell is connected to a row decoder through a wordline, to a column decoder through a bitline, and to a source decoder through a sourceline. Arranged in a path extending from a bitline to a sourceline through a transistor is an anisotropic resistance section, e.g., a diode, exhibiting different voltage-current characteristics for different levels of voltages applied thereacross. Because of such arrangement, leakage current occurring to a deselected memory cell in a reading operation can be reduced or can be eliminated. Read errors due to leakage current can be avoided and the power consumption can be reduced.

REFERENCES:
patent: 3744036 (1973-07-01), Frohman-Bentchkowsky
patent: 5047981 (1991-09-01), Gill
patent: 5350938 (1994-09-01), Matsukawa

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