Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2000-04-03
2001-02-06
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S238000, C438S253000
Reexamination Certificate
active
06184045
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a DRAM cell arrangement, i.e. a memory cell arrangement with dynamic random access, and to a method for its production.
The development of DRAM cell arrangements is focused on increasing the packing density. Currently, in DRAM arrangements, what are known as single-transistor memory cells are employed almost exclusively. A single-transistor memory cell contains a transistor and a capacitor. The information is stored in the capacitor in the form of an electrical charge representing a logical quantity of 0 or 1. By the actuation of the transistor via a word line, this information can be read out via a bit line. The transistor is usually connected between the bit line and the capacitor (for example, see DE 195 19 160). In the readout of the information, the charge on a first capacitor electrode of the capacitor, which electrode is connected to the transistor, determines the voltage at the bit line. A second capacitor electrode, which is not connected to the transistor, is kept constantly at half the operating voltage. A voltage signal which is formed by the difference of the voltage at the bit line and half the operating voltage corresponds to the information. The charge at the second capacitor electrode remains unused.
U.S. Pat. No. 4,630,088 incorporated herein teaches a DRAM cell arrangement in which a capacitor is connected between a bit line and a transistor. The charge of a capacitor electrode which is connected to the bit line is utilized for the formation of a voltage signal to which the information corresponds.
In T. Inaba, et al, “250 mV Bit-Line Swing Scheme for a 1V 4 Gb DRAM,” 1995
Symposium on VLSI Circuits Digest of Technical Papers:
pp 99-100, a DRAM cell arrangement is proposed in which a transistor is connected to a first bit line and a capacitor is connected to a second bit line. A voltage signal to which the information corresponds is generated by the difference of the voltages of the two bit lines, and so in effect by the charges on the two capacitor electrodes. In the charging of the capacitors, the operating voltage is applied either at the first bit line or at the second bit line. At the respective other bit line, 0V is applied. The second bit line is arranged in a depression and serves as a capacitor electrode. The first bit line and the second bit line extend parallel to one another. Due to the utilization of both charges of the capacitor instead of one charge, and due to the described actuation of the bit lines in the charging of the capacitor, for the same strength of the voltage signal, a smaller operating voltage is necessary here than in the DRAM cell arrangements with only one bit line. A smaller operating voltage means less lost power and enables a higher packing density of the DRAM cell arrangement.
The patents DE 195 19 160 and DE 196 37 389 teach the creation of word lines of a DRAM cell arrangement in self-adjusted fashion, i.e. without the utilization of adjusting masks. For this purpose, parallel first trenches are created, which are narrowed by the depositing and etchback of material. Perpendicular to the first trenches, second trenches are created whose width conforms to the original width of the first trenches. The narrowed first trenches are accordingly narrower than the second trenches. Material is deposited and etched back to create the word lines, whereby word lines emerge, in self-adjusted fashion, which extend parallel to the second trenches and which surround transistors in annular fashion.
In Y. Nishioka et al, “Giga-Bit Scale DRAM Cell with New Simple Ru/(Ba, Sr)TiO
3
/Ru Stacked Capacitors Using X-Ray Lithography”,
IEDM
95: p. 903, a DRAM cell arrangement is described in which a transistor is connected between a capacitor and a bit line. The capacitor is arranged over the transistor. Separate capacitor electrodes are provided with a capacitor dielectric, at which a capacitor plate adjoins.
SUMMARY OF THE INVENTION
It is an object of the invention to propose a DRAM arrangement which can be produced with the packing density necessary for the 1 GBit generation. Furthermore, a method for the production of such a DRAM cell arrangement is proposed.
According to the invention, a DRAM cell arrangement and method for making the arrangement is provided wherein a capacitor has a first capacitor electrode, and edges of the first capacitor electrode have a capacitor dielectric. An upper bit line is connected to the capacitor and acts as a second capacitor electrode and which annularly surrounds the first capacitor electrode having the capacitor dielectric. A transistor is arranged beneath the capacitor and is connected to the first capacitor electrode. First trenches are arranged between neighboring first capacitor electrodes along the upper bit line and which are narrower than second trenches arranged between neighboring first capacitor electrodes situated transversely to the upper bit line.
In the DRAM cell arrangement of the invention, an upper bit line is arranged above the capacitor, and the capacitor is arranged above a transistor. Sides of a first electrode of the capacitor, which electrode is connected to the transistor, are provided with a capacitor dielectric. The upper bit line is adjacent at the capacitor dielectric and surrounds the first capacitor electrode in annular fashion. The upper bit line also serves as a second capacitor electrode. In the readout of a stored item of information, a charge on the second capacitor electrode generates a voltage signal to which the item of information corresponds.
It is advantageous if an additional lower bit line is provided. The transistor is then connected between the first capacitor electrode and the lower bit line. The upper bit line extends beneath and parallel to the upper bit line. By means of the utilization of two bit lines, a smaller operating voltage can be utilized, as mentioned above. Instead of reducing the operating voltage, the voltage signal can be enlarged. Furthermore, both the operating voltage can be decreased and the voltage signal can be enlarged.
If the lower bit line is forgone, a source/drain region of the transistor can be connected to a constant potential, which usually equals half the operating voltage.
Parallel first trenches are provided and second trenches which extend transversely to the first trenches are provided, which separate neighboring first capacitor electrodes and in which upper bit lines of the DRAM cell arrangement are arranged. The first trenches are arranged between first capacitor electrodes which are arranged in adjacent fashion along the upper bit line. The first trenches thus extend transversely to the upper bit line. The second trenches are arranged between first capacitor electrodes which are situated in adjacent fashion transversely to the upper bit line. The second trenches thus extend substantially parallel to the upper bit line.
The first trenches are narrower than the second trenches. The DRAM cell arrangement can be produced with a small processing expense compared to the prior art, while simultaneously achieving a higher packing density. Subsequent to the creation of the capacitor dielectric, an upper bit line is created in self-adjusted fashion in that material is deposited and etched. The thickness of the deposited material is such that it fills the first trenches but not the second trenches. It is etched until the bottom of every second trench is partially exposed. The upper bit line thus arises in self-adjusted fashion and parallel to the second trenches. It surrounds the first capacitor electrode in annular fashion. The self-adjusted creation is a procedural simplification, for one, since no lithographically structured masks are created. On the other hand, it enables an increase of the packing density, since the necessary consideration of justification tolerances, which follows from the utilization of masks, is forgone.
To create the first capacitor electrodes, a layer can first be created. The layer is structured by the first trenches and the second trenches. The first
Hofman Franz
Krautschneider Wolfgang
Risch Lothar
Roesner Wolfgang
Schiff & Hardin & Waite
Siemens Aktiengesellschaft
Tsai Jey
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