Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-06-13
2002-05-28
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S202000
Reexamination Certificate
active
06396149
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally directed to creating an alternative conductive path or metal option for a flip-chip. More specifically, the present invention is directed to altering an easily accessible low metal layer to affect a change in a high metal layer.
2. Background
Testing of the circuitry of an integrated circuit (IC) chip may reveal flaws in the design or manufacture. The IC circuitry may be modified after manufacture by a use of a focused ion beam (FIB) as is well known in the art. Depending on the supplemental gas injection, if any, a FIB may etch away a material layer and may or may not deposit new material for creating a connection between points in the circuitry.
An IC may include several conducting layers having separate circuit configurations based on respective functions. While a FIB may be used to etch through multiple layers, the aspect ratio of width to depth (typically between about three and ten) limits the practical applicability to the first few lower layers. Some IC designs employ several layers, and a high metal layer may be difficult to modify by a FIB due to the lower intervening layers.
Typically, metal options for modifying IC circuitry are implemented at higher layer metals after option changes are implemented, due to reduced process time and cost. However, during the testing and debug stage of IC design modification, the associated retooling requirements are not cost effective.
Accordingly, there exists a need for an efficient, simple and inexpensive method to modify a high layer in an IC during the silicon debug stage for the primary purpose of final design verification.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method provides a connecting path diversion through an upper layer of an integrated circuit by alteration of a connecting path through a lower layer of the integrated circuit. This method enables a circuit path in an integrated circuit to be modified in an accessible layer for testing before the modified circuit path is incorporated in a redesigned integrated circuit design.
In another aspect of the present invention, a modified multi-layer integrated circuit chip includes a connecting path formed in a lower layer and a substitute connecting path that is etched in the lower layer. Subsequently, the connecting path formed in the lower layer may be severed.
REFERENCES:
patent: 4685033 (1987-08-01), Inoue
patent: 5095352 (1992-03-01), Noda et al.
patent: 5288949 (1994-02-01), Crafts
patent: 5648826 (1997-07-01), Song et al.
patent: 5928769 (1999-07-01), Monma et al.
Dunn Helen
Heald Raymond A.
Jin Xiaowei
Kaku James M.
Lai Peter F.
Nguyen Cuong Q
Ritchie David B.
Sun Microsystems Inc.
Thelen Reid & Priest LLP
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