Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1998-01-15
2001-03-27
Ton, Dang (Department: 2732)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C429S302000
Reexamination Certificate
active
06208662
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to data communication systems and particularly to an interface between a data bus, which may be connected to or from part of a local area network, and a system which operates in an asynchronous transfer mode, which conveys data in virtual channels according to a time shared process which allows a multiplicity of different messages to be transmitted over a single path in a time-shared manner, the messages being in the form of packets composed of cells, there being no regular or prescribed spacing between the cells.
INTRODUCTION
Data may be prepared for transmission in asynchronous transfer mode by means of a segmentation and reassembly memory (SAR), such as that described in ‘TDC 1570 Specification rev. 2.36’ (Texas Instruments), under the control of a programmed data processor, and requires substantial random-access memory, organised as a multiplicity of addressable buffers, which store data packets before and during their transmission on the virtual channels made available by the SAR.
SUMMARY OF THE INVENTION
It is appropriate to organize the buffers used for assembling the packets in accordance with a distribution and recovery scheme. The present invention is concerned with an improved technique wherein a single integrated queue is employed for both the distribution of buffers for the reception of data packets for transmission in asynchronous transfer mode and the recovery of buffers when the data packets have been transmitted and the buffers are available for reuse.
In a system where free buffers are taken from a buffer distribution queue by various devices, the buffers, when used, are typically returned to a buffer recovery queue in a random order. The buffer recovery queue is monitored by a central resource and the buffers are moved from this queue to the free buffer distribution queue for reuse by the devices. Such scheme typically uses two pointers (say start and finish pointers) to control each queue. The buffer recovery queue has to be at least the size of the buffer distribution queue to guarantee that the devices can return the used buffers to the buffer recovery queue when they have finished using the buffers. By integrating both queues into one queue, the space required is only that of a buffer distribution queue. The pointers are more efficient, in that by incorporating an indicator, herein after called ‘own bit’, only one pointer is used by the buffer recovery queue. The issue of the size of the buffer distribution queue is also removed as the buffer recovery queue is overlaid on the buffer distribution queue. This guarantees that there is always space for used buffers to be returned to the buffer recovery queue.
Other features of the invention will be apparent from the detailed description which follows by way of example of the invention.
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Murphy Ciaran
O'Connell Anne
O'Neill Eugene
3Com Technologies
Nixon & Vanderhye P.C.
Ton Dang
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