Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
2001-02-14
2004-08-17
Shankar, Vijay (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Reexamination Certificate
active
06778168
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a video interface mechanism used for displaying an image on a display panel, more particularly to a method for displaying an image, a host system, a display apparatus, etc. used for driving a plurality of display panels and high definition panels through a distributed processing.
BACKGROUND OF THE INVENTION
Generally, an image is transferred to a display apparatus after it is processed by a graphics controller included in a host system, like a personal computer (PC). However, due to the progress of display apparatuses, such as the active matrix liquid crystal display (AMLCD) panel that has appeared in recent years, many different processing systems have appeared between host system and display apparatus. For example, in the case of such LCD panels that have a higher resolution and pixel count, there are super-high definition LCD panels whose resolutions and pixel counts are very high like QXGA (Quad Extended Graphics Array) (2048×1536 dots), QSXGA (Quad Super Extended Graphics Array) (2560×2048 dots), QUXGA (Quad Ultra Extended Graphics Array) (3200×2400), etc. In addition, such display apparatuses as LCD panels are have smaller and smaller in-frame screen, so as to enable so-called tiling that groups a plurality of panels into an extended panel. As a result, in the display apparatus, a resolution can be increased to form a super-high definition panel.
And, now that the resolutions of those panels are improved significantly as described above, prior system powers and graphics controller powers cannot keep up with the progress of those panels. Consequently, it is impossible now to display image data satisfactorily on such super-high definition panels and multiple panels.
For example, the performance of such an image processing system as a graphics controller with general display functions is limited to QXGA or so. For such three-dimensional (3D) computer graphics (CG) as home video game machines, its processing capacity is as low as VGA (Video Graphics Array) (640×480 dots) in resolution. As described above, therefore, although the resolution of the latest dynamic picture images is VGA or so, LCD panels are manufactured so as to cope with resolutions several times to several tens of times that of the VGA. And accordingly, a significant difference has become apparent in processing capacity between host system and display apparatus.
And, if, when video data transferred from a host PC (host side) is displayed on a super-high definition display panel, the display panel attempts to keep the same frame rate as that of the host PC, then the transfer rate in the video interface must be increased in proportion to the high resolution of the display panel. On the other hand, in recent years, the video interface between a host PC and a display panel is rapidly shifted from the conventional analog interface to a so-called digital interface that employs a low voltage driving type digital data transmission method referred to as the LVDS (Low Voltage Differential Signaling), the TMDS (Transmission Minimized Differential Signaling) and the GVIF (Gigabit Video InterFace). Consequently, the transfer clock of this digital interface is improved and the number of signals of the video interface is increased to double (Dual Channel) and 4 times (Quadruple Channel), thereby enabling their transfer rates to be increased.
However, those methods have been confronted with a problem that each time a new super-high definition display panel appears, the transfer rate must be updated to its required one. Concretely, it is required that a new video interface timing is defined, a new LSI is developed so as to cope with the high transfer clock rate, and a new multiple channel structure is employed for the video interface signals in accordance with such a new display panel. It has also been required that those new items are added to such video interface standards as the VESA (Video Electronics Standard Association), etc. Those problems are not eliminated as long as the methods stick to those conventional video interface techniques. And, in order to solve those problems fundamentally, a video interface must be developed on the basis of a concept completely different from any of those conventional video interfaces.
Under such circumstances, this applicant has proposed a video interface as disclosed in Japanese Patent Application No. 11-341462. The disclosure describes a technique that enables distributed processings of an image between the host system and the display, where packetized video data is transferred. The amount of transfer data is reduced with respect to a transfer error detected in the data part.
According to the conventional techniques as described above, ACK (Acknowledge) and NACK (Not Acknowledge) are generally used to confirm sending/receiving of data during a transfer of packetized data. This ACK/NACK is returned as a confirmation answer from the receiver in response to each received packet. ACK is returned to the transmitter in response to correct receiving of a packet. Otherwise, NACK is returned to the transmitter. If, when transferred packetized video data is to be displayed on a panel (display side), video data is refreshed and transferred continuously, then neither ACK nor NACK is required. This is because video data is transferred again just after a transfer error if such a transfer error occurs. However, if display data is kept as is, the transfer cannot be stopped even in an error-free state. Thus, video data cannot be displayed normally unless it is rewritten. If an error occurs, therefore, the error must be notified with ACK/NACK, etc. For example, in the asynchronous sub-action transfer mode, which is a typical packet transfer mode of the IEEE1394 Standard, a bus master that has occupied a bus through an arbitration, after transferring an asynchronous packet to a slave bus target, must read back the acknowledge packet in a predetermined time gap. If such a transfer method is employed, it is possible to notify the host system of each error state. However, the average data transfer rate from the same bus master is degraded significantly at this time.
The Japanese Patent Application No. 11-341462 also describes the handling of an error that occurred in a data part during a packet transfer in an interface using neither ACK nor NACK or very slow ACK and NACK. According to the disclosure, it is possible to handle an error that occurred in a data part with efficiency. The transfer of mass image data included an added ID from the host system. In this case, however, it is impossible to recognize an error-occurred packet (a header ID transfer error) correctly when the system has a plurality of display panels. If such an ID error occurs, the packet may disappear before the error-occurred packet is identified.
Assume now that, for example, each line data is packetized and transferred. If an error occurs in the ID of a packet, then the address in the vertical address is increased sequentially so as to calculate a write address automatically. In such a case, the screen is deviated by one line from the error-occurred line. In addition, when image data is written at random, the data might not be written. Especially, if a plurality of display panels are used, it is impossible to identify the object display panel to process. Thus, there is no way for processing the error-occurred packet.
Under such circumstances, it is an object of the present invention to solve such the conventional technical problems and enable distributed processings to be made both at the system side and at the display panel side in such an advanced system as a super-high definition (QXGA, QUXGA, etc.) panel and a multiple panel and in a system for displaying information including text, image data, etc., thereby bringing out the maximum display processing ability.
It is another object of the present invention to enable transfer error handling by recognizing a transfer skip while image data is transferred from the host system.
It is still another object of
Mamiya Johji
Tomooka Takatoshi
Yamauchi Kazushi
Dharia Prabodh M.
Jennings Derek
Tuchman Ido
LandOfFree
Method for displaying image, image display system, host... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for displaying image, image display system, host..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for displaying image, image display system, host... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3330002