Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2002-12-19
2004-11-02
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S185230, C365S189090
Reexamination Certificate
active
06813216
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for discharging a word line, and more particularly, to a method for discharging a word line in which a negative voltage is stably maintained in a negative word line structure, and a semiconductor memory device using the same.
2. Description of the Related Art
A dynamic random access memory (DRAM) requires a refresh operation so as to maintain data (or charge) that is stored in a memory cell capacitor. A negative word line structure has been developed to improve the refresh characteristics of the DRAM.
In order to maintain word lines in a precharge or standby state at a predetermined negative voltage in the negative word line structure, a negative voltage generator is required. In a case where the negative voltage is unstable, the refresh characteristics deteriorate, and thus it is most important to stably maintain the negative voltage in the negative word line structure.
FIG. 1
is a block diagram of a conventional row address decoder. A main row decoder
20
activates a main word line select signal WEI
1
or WEI
2
in response to a second address ADDR
2
~
8
, and a sub row decoder
10
activates a sub word line select signal PXID
1
, PXI
2
, PXI
3
, or PXI
4
in response to a first address ADDR
0
~
1
.
A PXID generator
31
outputs a delayed sub word line select signal PXID
1
and an inverted sub word line select signal PXIB
1
in response to the sub word line select signal PXI
1
to sub word line drivers
33
and
35
.
The sub word line driver SWD
1
33
drives a word line WL
1
in response to the main word line select signal WEI
1
and the sub word line select signals PXID
1
and PXIB
1
.
In addition, the sub word line driver SWD
5
35
drives a word line WL
5
in response to the main word line select signal WEI
2
and the sub word line select signals PXID
1
and PXIB
1
.
Thus, the PXID generator
31
and the sub word line driver
33
constitute a word line select circuit
30
. The PXID generator
31
is positioned in a conjunction region, and the sub word line drivers
33
and
35
are positioned between memory array blocks.
Operation of the other PXID generators and sub word line drivers in
FIG. 1
is similar to that of PXID generator
31
and sub word line driver
33
, and thus a detailed description thereof is omitted.
FIG. 2
is a circuit diagram of the word line select circuit
30
of FIG.
1
.
FIG. 3
is a timing diagram for operation of circuit
30
shown in FIG.
2
. Referring to
FIGS. 1 through 3
, PXID represents a signal by which the level of a word line WL is determined and a boosting voltage VPP is supplied to the word line WL, the PXID signal swings between the boosting voltage VPP and a negative voltage VNN.
The boosting voltage VPP is higher than a supply voltage VCCA that is supplied to a semiconductor memory device and is output from a boosting voltage generator (not shown) in the semiconductor memory device.
As shown in
FIG. 3
, the discharge level of control signals WEI, PXID, and PXIB for controlling the sub word line driver
33
is the negative voltage VNN. If the load on a PXID line is large, the semiconductor memory device requires a large-capacity negative voltage VNN generator (not shown) so as to smoothly discharge the control signal PXID.
When the level of the sub word line select signal PXI transitions from the boosting voltage VPP to the negative voltage VNN, most of the discharge current of the PXID, that is, the discharge current of the word line WL, is discharged to the negative voltage VNN through an inverter in the PXID generator
31
.
A transistor
3
is turned on in response to the control signal PXIB, and the PXID, along with the word line WL, are discharged from the level of the boosting voltage VPP to the level of the negative voltage VNN through the transistor
3
. Thus the discharge current of the PXID is rapidly flowed into the negative voltage VNN generator. Accordingly, the negative voltage VNN becomes unstable, and therefore the refresh characteristics deteriorate.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for discharging a word line in which a negative voltage is stably maintained using the voltage level of a PXID or word line WL, and a semiconductor memory device using the same.
According to one embodiment of the present invention, there is provided a method for discharging a word line, the method comprising discharging the word line to a first power supply through a first switch that is connected to the word line until the first switch reaches a threshold voltage, and simultaneously, discharging the word line to a second power supply through a second switch that is connected to the word line, and then discharging the word line to the second power supply through the second switch after the first switch reaches the threshold voltage.
According to another embodiment of the present invention, there is provided a method for discharging a word line, the method comprising discharging the word line to a first power supply through a first switch that is turned on in response to the voltage of the word line, and simultaneously, discharging the word line to a second power supply through a second switch that is connected to the word line, and then discharging the word line to the second power supply through the second switch after the first switch is turned off in response to a reduction in voltage on the word line.
According to another embodiment of the present invention, there is provided a method for discharging a word line, the method comprising discharging current from the word line to a first power supply through a first current path that is formed in response to a predetermined word line select signal and the voltage of the word line, and simultaneously, discharging current from the word line to a second power supply through a second current path that is formed in response to the word line select signal, and discharging current from the word line to the second power supply through the second current path when the first current path is blocked in response to a reduction in voltage on the word line.
According to another embodiment of the present invention, there is provided a semiconductor memory device. The semiconductor memory device includes a word line, a first switch that is connected between the word line and a first power supply and discharges current from the word line to the first power supply in response to a word line select signal and the voltage of the word line, and a second switch that is connected between the word line and a second power supply and discharges current from the word line to the second power supply in response to the word line select signal.
According to another embodiment of the present invention, there is provided a semiconductor memory device. The semiconductor memory device includes a word line, a transistor that is connected between the word line and a first power supply and discharges current from the word line to the first power supply in response to a word line select signal and the voltage of the word line, and a second switch that is connected between the word line and a second power supply and discharges current from the word line to the second power supply in response to the word line select signal.
According to another embodiment of the present invention, there is provided a semiconductor memory device. The semiconductor memory device includes a word line, a first pull-up circuit for pulling up the word line to the level of a boosting voltage in response to a word line select signal, a first node, a switch for connecting the first node to the word line in response to the word line select signal, a first pull-down circuit for pulling down the word line to the level of a ground voltage in response to the voltage at the first node, and a second pull-down circuit for pulling down the word line to the level of a negative voltage in response to the word line select signal. The first pull-down circuit is deactivated when the voltage at the first node bec
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