Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area
Patent
1995-01-20
1997-04-01
Gorgos, Kathryn
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating selected area
205126, 205159, 205162, 205163, 205164, 205165, 205166, 205183, 205205, 205210, C25D 502, C25D 554, C25D 556, C25D 534
Patent
active
056162308
DESCRIPTION:
BRIEF SUMMARY
This is a 371 of PCT/JP94/00826 filed May 24, 1994.
TECHNICAL FIELD
This invention relates to a technology for direct-electroplating an electrically nonconductive substrate. This technology is suited for the direct electroplating of the walls defining through-holes of a printed circuit board, for instance.
In this specification, "%" means "% by weight".
BACKGROUND ART
In through-hole plating for the manufacture of a printed circuit board, the subtractive process is most frequently utilized. The subtractive process comprises drilling through-holes in a substrate consisting of an insulating board and a copper foil cladding disposed on either side thereof, causing a thin electroless copper plate to precipitate on the nonconductive walls defining the through-holes to render them electrically conductive, and depositing a thick copper electroplating layer to establish electrical connection between the copper foils and thereby complete an electric circuit.
This is a reliable technology well-established and use-tested over about a couple of decades. However, this process involves electroless plating as an essential step and this step requires a complicated pretreatment for rendering the nonconductive surfaces electrically conductive. The plating solution for use in electroless plating is so self-decomposing as to call for meticulous control over the bath composition. Moreover, as a reducing agent required for precipitation of copper, the use of formaldehyde which is a highly toxic material is essential. A further disadvantage of the process is that it takes a long time even to attain quite a thin copper layer.
DISCLOSURE OF INVENTION
The principal object of this invention, therefore, is to provide a technology for rendering nonconductive areas electrically conductive by mere copper electroplating without resort to electroless copper plating which is a major technical drawback of the prior art, which technology provides for improved productivity through process simplification, reduction of processing time and improved working environment.
In view of the state of the art sketched above, the inventors of this invention did much research and found that the above-mentioned object can be accomplished by using certain processing steps in a specific combination. The inventors further discovered that this specific combination of steps can be applied with advantage to the direct formation of copper electroplating layers on nonconductive substrates in general.
This invention, therefore, provides the following processes.
1. A process for plating an electrically nonconductive substrate characterized in that said substrate is treated in the following sequence of steps: solution containing a silane coupling agent; step (1) with a solution containing an anionic surfactant; step (2) with a solution containing a palladium compound and at least one nitrogen-containing sulfur compound selected from among thiourea and its derivatives; from said step (3) with a reducing solution containing at least one member selected from among sodium borohydride, sodium hypophosphite, hydrazine, dimethylaminoborane, hydroxylamine and glyoxylic acid; and nonconductive substrate from said step (4).
2. The plating process as defined above in item 1 wherein the concentration of palladium ion in the treating solution for use in said step (3) is 0.1-10 g/l and the concentration of said nitrogen-containing sulfur compound is 1-50 moles per mole of said palladium ion.
3. The plating process as defined above in item 2 wherein said nitrogen-containing sulfur compound is any of thiourea, thioacetamide, thiosemicarbazide and dimethylthiourea.
4. A through-hole plating process for a printed circuit board characterized in that a double-sided printed circuit board or a multi-layer printed circuit board is treated in the following sequence of steps: board with a solution containing a silane coupling agent; solution containing an anionic surfactant; solution containing a palladium compound and at least one nitrogen-containing sulfur compound selected from am
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patent: 4255194 (1981-03-01), Hough et al.
patent: 4316779 (1982-02-01), Yahalom
patent: 4810333 (1989-03-01), Gulla et al.
patent: 4873136 (1989-10-01), Foust et al.
patent: 4988413 (1991-01-01), Chakravorty et al.
Konishi Satoshi
Otsuka Kuniaki
Yamamoto Kazue
Yamato Shigeru
Gorgos Kathryn
Okuno Chemical Industries Co. Ltd.
Wong Edna
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