Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1998-06-18
2001-07-03
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S433000, C438S420000, C438S554000, C438S558000, C438S561000, C438S563000
Reexamination Certificate
active
06255190
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to produce dielectrically isolated, very deep pn-junctions in a silicon substrate without the use of epitaxy or extensive high temperature processing, but using deep trench sidewall predeposition technology. The principle of the invention consists in the formation of at least two parallel deep trenches and the rather uniform distribution of the doping material between said trenches by predepositing the sidewalls, filling the trenches with insulating material, and diffusing the predeposited dopants preferably simultaneous with the normal well diffusion of a CMOS process, in a manner that a subregion in the silicon substrate emerges, which pn-junction depth equals the trench depth plus the diffusion depths. That means that counterdoped regions which are more deep than wide are possible to be realized.
The invention relates to the integration of high voltage and preferably small signal transistors into integrated circuits (IC's) on monocrystalline silicon wafers.
The most widely spread method of isolating the individual transistors on the integrated circuit one to each other is the formation and use of negatively biased pn-junctions. On both sides of a negatively biased pn-junction a depletion layer, or space charge region of a certain thickness builds up. Within this layer the voltage drop between the two sides of the pn-junction occurs, and therefore an electric field exists, dependent on the voltage difference and the depletion layer width.
The higher the doping level on each side of the pn-junction is, the smaller is the depletion layer width, and, at a given voltage difference, the higher is the electric field. On contrary to that the critical electric field, i.e. the field where voltage breakdown due to avalanche multiplication occurs, is almost independent of the dopant concentration. Thus the higher the operating voltage of an IC, or a part of an IC is, the more space is needed in order to prevent breakthrough of the transistors in the off-state, and also, in the case that the transistor should be floating, to prevent breakthrough between the transistor and ist vicinity.
Conventional processing of regions counterdoped to a substrate, on an epitaxial layer or a former formed well implies predepositing the dopant atoms in concentrated phase at or near the surface and subsequently diffusing them with a high temperature process. Every such process implies that the lateral diffusion width is approximately but at least as wide as the diffusion width perpendicular to the wafer surface.
Reminding that there are two purposes of a high voltage pn-junction, namely first forming the channel-drain junction of a MOS transistor or forming the base-collector junction of a bipolar transistor etc., and second providing the device isolation it must be emphasized that the first purpose must be realized by a pn-junction, whereas for the second purpose alternatives exist.
SUMMARY OF THE INVENTION
After having stated these fundamental boundary conditions the scope of the invention can be explained to be the following:
In order to save space on the IC the claimed invention is a structure where the depletion layer width which serves as the active part of the transistor, i.e. the pn-junction where the main voltage drop during the off-state occurs, is placed in the direction perpendicular to the wafer surface and the purpose of the lateral transistor isolation is achieved with oxide filled trenches rather than pn-junctions, whereas the transistor isolation downwards to the substrate remains a junction. Since the critical electric field prior to breakdown in silicon is approximately 0.3 MV/cm and that in silicon dioxide is approx. 8 MV/cm, a lateral dielectric isolation of devices clearly is advantageous over junction isolation.
A similar concept is known in sparks, U.S. Pat. No. 5,250,461, but epitaxy equipment is necessary to realize what is claimed there:
What is claimed in this invention is a method to achieve the goal of transistor structures with active pn-junctions vertical to the surface and lateral dielectric isolation, thus a transistor structure which can lead to devices essentially more deep than wide, without the use of epitaxy machines and very high temperature furnaces.
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Austria Mikro Systeme International AG
Dang Trung
Wilson Sonsini Goodrich & Rosati
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