Semiconductor device manufacturing: process – Semiconductor substrate dicing
Reexamination Certificate
2000-02-10
2002-04-16
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
C438S464000, C438S465000, C438S033000, C438S113000
Reexamination Certificate
active
06372610
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for die separation of a wafer by ion implantation, and more particularly, to a method for die separation, wherein the die spacing is reduced and the die separation precision reaches a sub-micron level.
2. Description of the Prior Art
Recently, die separation of brittle wafers has been a basic packaging operation essential for silicon-based semiconductor devices (such as ICs and solar cells) and opto-electronic semiconductor devices (such as LEDs and laser diodes). The general die separation process used nowadays is implemented by mechanical grinding with an electroplated cutting wheel or an electroplated dicing blade. Such knowledge is disclosed, for example, in U.S. Pat. No. 5,609,148, “Method and apparatus for dicing semiconductor wafers,” filed by Mitwalsky and Alexander at Siemens Aktiengesellschaft (Munich, DE), and Okumura and Katsuya at Kabushiki Kaisha Toshiba (JP), in which the wafer is bowed or bent by forcing it into contact with a spherical surface having parallel grooves therein and in which an array of parallel wire saws that are in registration with the grooves is forced against the wafer for sawing parallel channels therethrough.
Nevertheless, in the prior arts discussed above, die separation process is realized by using a mechanical grinding method, which has suffered from the following drawbacks.
1. The die spacing is always more than 20 microns, and more particularly, the die spacing accomplished by using an electroplated cutting wheel is more than 40 microns, therefore a considerable area on the wafer has to be preserved for die separation process when the layout is being designed. During the past two decades, the manufacturers have made lots of efforts to minimize the critical dimension in order to reduce the manufacturing cost and enhance their competence. However, due to the large area sacrificed for scribe lines that can not be further minimized, the number of separated dies is limited on each wafer and therefore the manufacturing cost can not be reduced.
2. The speed of die separation is low by mechanical grinding since the scribe lines are created one by one and can not be accomplished at the same time.
3. A great amount of contaminants and undesired particles may be generated during die separation by mechanical grinding with an electroplated cutting wheel and contaminate the device and thus reduce the yield.
4. For any substrate that has been deposited with thin films, there exists strain at the interface, due to the different lattice constants of the junction materials, which leads to warpage. For example, structures of more than twenty layers deposited on an 8-inch wafer and patterned to define the IC layouts that are used to accomplish complicated ICs such as microprocessors and DRAMs generally have a warpage value of tens of microns. Such 8-inch wafer may suffer from warpage larger than one hundred microns after back grinding process. Under strain and warpage to such level, die separation process by mechanical grinding usually leads to wafer cracking and greatly affects the yield.
Accordingly, die separation process realized by mechanical grinding has suffered from several problems that can not be solved. Therefore, it is urgent to develop other die separation techniques to replace mechanical grinding to avoid the mentioned drawbacks. On the other hand, M. Kaminsky proposed in IEEE Trans. Nucl. Sci. MS-18 (1971) 208 that gaseous ions implanted into metal lead to formation of micro-bubbles. Such knowledge was later used in the design of a nuclear reactor since the a particles, i.e. helium ions (He
+
), generated from the nuclear reactor constantly bombard the inner wall of the reactor and cause flaking or exfoliation of the wall metal, which strikes the nuclear industry heavily. For more detailed description, please refer to articles in Radiat. Eff. 53 (1980) 257 by S. K. Das and in Nucl. Instr. and Meth. 209/210 (1983) 333 by R. G. Saint Jacques.
Implanted gaseous ions do not only lead to metal flaking but also cause semiconductor exfoliation between layers. Such knowledge is disclosed, for example, in Nuclear Instruments and Methods in Physics Research B
108
(1996) 313-319 by M. Bruel and in Materials Science and Engineering B
46
(1997) 14-19 by C. Maleville. Hydrogen ion implantation into semiconductor wafer causes layer splitting after heat treatment and thus leads to formation of high quality silicon-on-insulator (SOI) structure. The principle of this process involves the basic mechanism associated with a mass of hydrogen ions implanted into semiconductor wafer. Thermal treatment leads to formation of micro-bubbles that swell and cause layer splitting of the semiconductor wafer.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method for die separation of a wafer by ion implantation.
Moreover, it is another object of the present invention to provide a method for die separation of a wafer by ion implantation, wherein the die spacing is reduced and the die separation precision reaches a sub-micron level.
In order to accomplish the foregoing objects, the present invention relates to a method for die separation of a wafer by ion implantation, wherein the die spacing is reduced and the die separation precision reaches a sub-micron level. The separated dies are obtained by wafer splitting after heat treatment and have cleavage roughness at a nano-meter level. The process method comprises the steps of: placing a wafer into an ion implanter; implanting gaseous ions into the split lines of said wafer with assistance of a mask, wherein said gaseous ions can be hydrogen ions or helium ions that do not chemically react with said wafer; performing heat treatment of said wafer that is to split at the split lines; and completing die separation.
Said heat treatment is carried out in the temperature ranging from 100 to 600° C., depending on the dosage of said gaseous ions. In order to meet the requirement for lower thermal budget, the temperature for heat treatment does not need to be high (lower than 250° C.) to make said wafer split when the dosage of the implanted gaseous ions is relatively high (higher than 1E17 cm
−2
). On the contrary, if the dosage of implanted gaseous ions is relatively low, higher temperature is required to make said wafer split.
The disclosure of the present invention is advantageous in that the die spacing is reduced and the die separation precision reaches a sub-micron level, which can enhance the competence of the products by a lower manufacturing cost resulted from a larger number of separated dies fabricated on each wafer. Moreover, in the method proposed in the present invention, die separation operation is processed at the same time, which avoids the wafer from cracking due to the prevention of strain caused by mechanical grinding, and furthermore, the yield can be improved.
REFERENCES:
patent: 5266528 (1993-11-01), Yamada
patent: 5374564 (1994-12-01), Bruel
patent: 5559043 (1996-09-01), Bruel
patent: 5609148 (1997-03-01), Mitwalsky et al.
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patent: 6271101 (2001-08-01), Fukunaga
patent: 2775831 (1998-03-01), None
patent: 01246875 (1989-02-01), None
Chang Fuh-Yu
Chang Shao-Heng
Lin Hung-Yi
Everhart Caridad
Industrial Technology Research Institute
Rocchegiani Renzo N.
Troxell Law Office PLLC
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