Method for developing shallow trench isolation in a semiconducto

Details Method for developing shallow trench isolation in a semiconducto Method for developing shallow trench isolation in a semiconducto

1997-09-04

1999-05-18

Tsai, Jey

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438435, 438443, 438447, H01L21/76

Patent

active

059045388

ABSTRACT:
A method for developing shallow trench isolation in a semiconductor device includes forming an ion diffusion area by implanting fluorine ions where a trench is to be formed in a semiconductor substrate before forming the trench, performing an annealing process or a tilt ion implantation process to diffuse the fluorine ions into both sides corresponding to the upper corners of the trench, wherein the fluorine implantation process increases the oxidation rate of the upper corners of the trench to be more than that of the semiconductor substrate when a light oxidation proceeds for preventing damage to the semiconductor substrate in forming the trench. Accordingly, the upper corner portions of the trench are formed to be rounded so as to distribute an electric field, thereby preventing a hump phenomenon when the completed semiconductor memory device is operated.

REFERENCES:
patent: 4523369 (1985-06-01), Nagakubo
patent: 4534824 (1985-08-01), Chen
patent: 4570325 (1986-02-01), Higuchi
patent: 5229316 (1993-07-01), Lee et al.

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