Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
1999-10-21
2001-07-10
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S016000, C438S401000, C430S312000, C430S394000, C430S396000
Reexamination Certificate
active
06258611
ABSTRACT:
TECHNICAL FIELD
The present claimed invention relates to the field of semiconductor wafer fabrication. More specifically, the present claimed invention relates to a method for determining the translation portion of misalignment error in a stepper used to fabricate patterned layers on a wafer.
BACKGROUND ART
Integrated circuits (ICs) are fabricated en masse on silicon wafers using well-known photolithography, etching, deposition, and polishing techniques. These techniques are used to define the size and shape of components and interconnects within a given layer of material built on a wafer. The IC is essentially built-up using a multitude of interconnecting layers, one formed on top of another. Because the layers interconnect, a need arises for ensuring that the patterns on adjacent layers of the wafer are accurately formed.
Referring now to prior art
FIG. 1A
, a side view of a stepper is shown. A stepper
100
a
includes a light source
122
, masking blades
124
, a reticle
126
, a lens
128
, and a stage
132
. The light source
122
projects light through an opening
126
a
of masking blades
124
, through the transparent portion of a pattern on a reticle
126
A, through lens
128
and onto a wafer
133
, located on the stage
132
. By doing so, the pattern of the reticle
126
is reproduced on the wafer
133
, typically at a 5:1 reduction. A pattern located on an inner, or center, portion
126
a
of the reticle
126
, passes through a center portion
128
a
of lens
128
. Similarly, a pattern located on an outer, or peripheral, portion
126
b
of the reticle
126
, passes through an outer portion
128
b
of lens
128
.
Accurate formation of an image on a wafer using photolithography depends on several error-causing variables. These variables include rotational alignment error, translational alignment error, lens distortion error, and reticle writing error, among others. One of the most important variables for accurate formation of an image on a wafer is translational alignment error, or translational misalignment. The alignment error, arises between the reticle image, projected within the stepper, and the actual image formed on the wafer while in the stepper. Precise alignment between the succeeding layers formed on the wafer is critical for several reasons. For example, precise alignment is necessary to accurately couple interconnects, to ensure proper location of insulators, and to accurately shape and size devices for proper performance. The alignment system used in a stepper can cause a linear off-set, or translational misalignment in the X and Y direction, for a Cartesian-coordinate based system. Hence, a need arises for ensuring accurate translational alignment of multiple layers formed on a wafer.
Each one of the error-causing variables can be corrected by a different part of the stepper. If errors are not segregated and measured independently, then the error measurements are confounded, and the resulting corrections for each variable may be contradictory and self-defeating. Thus, a need arises for a method to segregate other error-causing variables from the translational misalignment variable to yield a true translational misalignment measurement.
Referring now to prior art
FIG. 1B
, a top view of a conventional alignment reticle is shown. Alignment reticle
126
includes a first overlay box
130
a
, a second overlay box
130
b
, both located at the center portion of the reticle
126
, and a fine alignment target
132
located at an outer portion of the alignment reticle
100
b
. Hence, the fine alignment target is located a significant distance,
136
and
138
, away from small overlay box
130
a
and large overlay box
130
b
. Large overlay box
130
b
is offset from small overlay box
130
a
by a distance
140
. Alignment reticle
126
of prior art
FIG. 1B
is shown in a side view in prior art FIG.
1
A.
The conventional alignment reticle and alignment process is corrupted by including errors other than translation misalignment errors in the process. The conventional process creates an alignment target at an outer location of the reticle image,
132
of prior art
FIG. 1B and 126
b
of prior art
FIG. 1A
, that is projected through an outer portion
128
b
of the lens
128
of prior art FIG.
1
A. Consequently, the alignment target created on the wafer suffers from lens distortion. Lens distortion typically increases towards the outer regions of the lens, due to factors such as lens irregularities and to properties of light. Additionally, the alignment target created on the wafer suffers from reticle writing error because it located a significant distance, e.g.
136
and
138
of prior art
FIG. 1B
, away from the overlay boxes, e.g.
130
a
and
130
b
, used to measure the misalignment of the stepper. That is, reticle writing error can have an error rate, linear or exponential, that accumulates over the distance between two images on the reticle. Hence, if an overlay box is located far away from an alignment target, then the prior art misalignment check will be measuring the translational misalignment of the reticle along with the translational misalignment of the stepper.
Furthermore, a long distance between the overlay boxes and the alignment targets only serves to amplify any processing error for the steps used in the alignment process, e.g. offset-measurement error. For example, if the wafer is realigned in the stepper using a charge coupled device (CCD) and digital signal processing pattern matching with a given tolerance, then this tolerance may be amplified at a location far from the alignment target. In one instance, a given rotational error at the alignment will increase with the distance, or radius, from the alignment target. This scenario is shown in the following figure, prior art FIG.
1
C. Consequently, a need arises for creating an error-free alignment target. More specifically, a need arises for creating an alignment target without reticle writing error, offset-measurement error, and lens distortion error.
Referring now to prior art
FIG. 1C
, an example of a preventative maintenance wafer with overlay boxes created therein is shown. One shot
150
on a wafer is shown in this figure. Shot
150
has a small alignment box
160
a
and a large alignment box
160
b
, and a fine alignment target
162
formed therein. Alignment reticle
126
of prior art
FIG. 1B
is used to create the overlay boxes on the wafer
150
. However, in this example, a misalignment other than translational error occurs when the stepper did not accurately align to fine alignment target
162
, for the process that formed the second overlay box
160
b
on wafer
150
. Even though the rotational error during alignment was a small angle
164
, the large distance
166
between fine alignment target
162
and overlay box
160
a
magnifies the error to a substantial X error
162
and Y error
164
. Hence, rather than correcting the small error in rotation, the prior art may attempt to correct the stepper with a misalignment correction in the X direction of
162
and a misalignment correction in the Y direction of
164
. Consequently, the prior art alignment reticle and misalignment measurement process may actually overcorrect the stepper and possibly cause more error than originally existed.
The confounding of errors in the prior art translational misalignment measurement process becomes important when considering budget overlay requirements. Budget overlay is a value associated with the allowable tolerance for manufacturing a given size of photolithography imprint. For example, a 0.2 micron technology would typically have a 0.08 micron budget overlay. However, as demand increases for smaller and smaller images, the budget overlay must decrease as well. For example, the current 0.12 micron technology only allows approximately a 0.055 micron budget overlay. Consequently, as budget overlay decreases, the error in the misalignment measurement becomes more significant. Thus, a need for improving the accuracy of the translational misalignment measurement arises in light of more strin
Luk Olivia
Niebling John F.
VLSI Technology Inc.
Wagner , Murabito & Hao LLP
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