Method for determining transistor gate oxide thickness

Details Method for determining transistor gate oxide thickness Method for determining transistor gate oxide thickness

2000-08-08

2002-09-24

Le, N. (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S765010, C438S016000

Reexamination Certificate

active

06456105

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor fabrication, and more particularly to methods for determining MOS transistor gate oxide thickness.
BACKGROUND OF THE INVENTION
Semiconductor chips or wafers are used in many applications, including as processor chips for computers, and as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices.
A common circuit component of semiconductor chips is the transistor. In ULSI semiconductor chips, a transistor is established by forming a polysilicon gate on a silicon substrate, and then forming a source region and a drain region side by side in the substrate beneath the gate by implanting appropriate dopant materials into the areas of the substrate that are to become the source and drain regions. The gate is insulated from the source and drain regions by a thin gate oxide layer that has a thickness of a few to several tens of Angstroms. This generally-described structure cooperates to function as a transistor.
It is important from the standpoint of process control that the electrical thickness of the gate oxide layer be precisely known. For instance, if a gate oxide layer is designed to be only 15 Å thick, deviations from the design thickness must be detected so that the process can be appropriately adjusted to avoid making MOS transistors that do not perform according to specification, and/or that perform unreliably.
The present invention recognizes that one way to measure the electrical thickness of a gate oxide layer is by measuring the gate capacitance as a function of gate voltage, and then using the capacitance at the desired gate voltage to determine the electrical thickness of the gate oxide layer. As further recognized herein, however, as the thickness of the gate oxide becomes very small, as is the trend in semiconductor manufacturing, the leakage current caused by electrons tunnelling through the oxide increases dramatically. This increases the parasitic resistance of the device and consequently makes it difficult if not impossible to accurately determine a capacitance using conventional methods, hence rendering the computation of oxide electrical thickness problematic.
The phenomenon of increased tunnelling leakage current in very thin gate oxide layers is noted in Yang et al., “MOS Capacitance Measurements for High-Leakage Thin Dielectrics”, IEEE vol. 46 (July, 1999). Unfortunately, Yang et al. does not teach how to extract gate oxide electrical thickness, a shortcoming that the present invention addresses.
BRIEF SUMMARY OF THE INVENTION
A method is disclosed for determining the electrical thickness of a gate oxide layer of a MOSFET. The method includes measuring at least one measured capacitance, and using the measured capacitance, rendering a first capacitance. Then, using the first capacitance, the electrical thickness is determined.
In a specific embodiment, two measured capacitances, one each at a respective frequency, are measured for each of a plurality of gate voltages. In essence, the first capacitance is a leakage-current corrected capacitance. In a broader sense, however, the first capacitance is simply a capacitance that is derived from one or more, preferably two, measured capacitances C
1
, C
2
.
To render the first capacitance, a ratio of the difference between first and second frequency-dependent terms to the difference between the squares of first and second frequencies is determined. More specifically, the first capacitance C={[f
1
2
C
1
(1+D
1
2
)]−[f
2
2
C
2
(1+D
2
2
)]}/{f
1
2
−f
2
2
}, wherein f
1
is the first frequency, f
2
is the second frequency, D
1
is a first dissipation associated with the first frequency, and D
2
is a second dissipation associated with the second frequency. The electrical thickness is an inverse function of the first capacitance.
Other features of the present invention are disclosed or apparent in the section entitled “DETAILED DESCRIPTION OF THE INVENTION”.


REFERENCES:
patent: 5485097 (1996-01-01), Wang
patent: 5757204 (1998-05-01), Nayak et al.
Kevin J. Yang & Chenming Hu: “MOS Capacitance Measurements For High-Leakage Thin Dielectrics.” IEEE Transactions On Electron Devices; vol. 46, No. 7, Jul. 1999; pp. 1500 & 1501.

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