Method for determining timing delays associated with placement a

Details Method for determining timing delays associated with placement a Method for determining timing delays associated with placement a

1994-05-16

1997-05-13

Teska, Kevin J.

Boots, shoes, and leggings

G11C 702

Patent

active

056298609

ABSTRACT:
The present invention provides a method for determining timing delays associated with the placement and routing delays of an integrated circuit. In particular, the present invention determines the area of each region wherein a region includes a group or subgroup of circuit elements for use in designing an integrated circuit. Once the area for each region is obtained, substantially more accurate and more design specific wireload model and net parasitics can be obtained. The wireload models or net parasitics can then be supplied to other CAE tools to create a modified netlist. Moreover, the present invention provides a process which allows the user to account for the RC time constant effects of wire delay on a hierarchical block basis thereby improving the accuracy of the wire placement and routing delay estimate while preserving the performance benefits of a traditional simplified equation.

REFERENCES:
patent: 4922432 (1990-05-01), Kobayashi et al.
patent: 4967367 (1990-10-01), Piednoir
patent: 4978664 (1990-12-01), Bell
patent: 5084824 (1992-01-01), Lam et al.
patent: 5111413 (1992-05-01), Lazansky et al.
patent: 5175693 (1992-12-01), Kurosawa et al.
patent: 5278769 (1994-01-01), Bair et al.
patent: 5452224 (1995-09-01), Smith, Jr. et al.

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