Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-07-23
2001-03-06
Brown, Glenn W. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010
Reexamination Certificate
active
06198301
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to a method for determining certain characteristics of a transistor, and more specifically, to a method for determining the hot carrier lifetime of a transistor.
BACKGROUND OF THE INVENTION
During manufacturing of semiconductor devices, such as transistors, quality control monitoring is implemented to ensure that the fabricated devices are conforming to their design specifications. Typically, the device characteristics, e.g., substrate current (I
sub
), current drain saturation (I
DSAT
), or, current in the linear region (I
DLIN
), etc. are monitored and compared to a predetermined value that is used as a standard. This provides a means of detecting problems and/or failures as early in the fabrication process as possible, to minimize further manufacturing costs. Furthermore, these tests provide early warning of reliability problems to the semiconductor device manufacturers and ultimately help to characterize, benchmark and improve the reliability and quality of the semiconductor integrated circuits (ICs) and processes. It is, therefore, desirable that these tests can be conducted both accurately and quickly to provide the fabrication lines with reliable current feedback.
Although different devices generally have different benchmark standards associated with them, there are certain tests that are universally employed by all these devices. For example, tests that help characterize major IC failure mechanisms, which include oxide integrity, electromigration and transistor degradation, are usually utilized regardless of the device type being fabricated.
Transistor degradation characterization is typically defined using a particular device's hot carrier lifetime. As process geometries shrink, electric fields present within semiconductor devices increase, since the distances, across which electrical potentials act, are diminished. The resultant high magnitude electric fields generate hot carriers that are electrons accelerated to relatively high velocities. A hot carrier lifetime is typically a measurement of the length of time it takes for a semiconductor device to degrade an arbitrary amount. Testing involves monitoring the change in a device characteristics under accelerated bias conditions. Failure is defined as the time when a percentage change, e.g., 15%, in the device characteristic under test. A common device characteristic that is used to determine hot carrier lifetime is linear transconductance (g
m
). In most applications, the hot carrier lifetime is determined along with the other above-mentioned tests. For example, an initial transconductance measurement, in conjunction with other test measurements, is taken and is then followed by stressing the device and then taking different test measurements again, such as I
DSAT
. Subsequent to these measurements, another transconductance measurement is then taken.
Under these present methods, determining the hot carrier lifetime of a device using the degradation of the device transconductance characteristic generally requires either a significant amount of time or a substantially increased voltage above the operating voltage which could be near the breakdown voltage of the device. Depending on the percentage degradation criteria used, e.g., 10% or 15%, the testing (repeated measurement and stress) period may last as long as 100 hours. These long periods of time are, of course, highly undesirable where “real-time” feedback is needed to keep the quality of the device consistently high.
One common approach to reducing the time period is to increase (substantially above the device's operating voltage) the bias, or stress, voltages applied to the device. Using high stress voltages, however, does not truly reflect the conditions seen by the device in common usage. More significantly, the time required to determine the hot carrier lifetime essentially precludes its use during the fabrication process. Instead, current manufacturing determination of a device's hot carrier lifetime involves measuring the device's I
sub
characteristic and comparing the measured value with a predetermined value. Unfortunately, however, comparing the value I
sub
to a baseline value only provides an approximation, since there is no exact correlation between I
sub
and hot carrier lifetime. Furthermore, as a device's process changes, these changes can affect the device I
sub
characteristic. In which case, the baseline I
sub
standard used in the manufacturing process must also be recalculated. Therefore, as it can be seen from the foregoing, the present methods of determining hot carrier lifetimes of transistor devices lack the accuracy and the short determination times desired in the fabrication process.
Accordingly, what is needed in the art is an improved method for determining a device hot carrier lifetime with greater accuracy and for determining a device hot carrier lifetime that is accomplished in a shorter period of time and uses stress voltages that are closer to the device's operating voltage.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a method for determining a hot carrier lifetime of a transistor. In one embodiment, the method comprises determining an initial transistor characteristic of the transistor that is affected by hot carrier aging; then applying a stress voltage to the transistor to cause the initial transistor characteristic to change wherein the stress voltage does not exceed a maximum breakdown voltage of the transistor; and then determining a change in the initial transistor characteristic, with a hot carrier lifetime of the transistor being a function of initial transistor characteristic and the change in the initial transistor characteristic. In another aspect of this particular embodiment, determining an initial transistor characteristic includes determining an initial transconductance (g
m1
) of a transistor, and then, applying a stress voltage, which does not exceed a maximum breakdown voltage of the transistor, to the transistor to cause a transconductance degradation of the transistor, and then determining a subsequent transconductance (g
m2
) of the transistor. A hot carrier lifetime of the transistor can then be determined as a function of g
m1
and g
m2
.
Thus, the present invention provides a method in which the hot carrier lifetime is determined from sequential transconductance measurements without intervening, other transistor characteristic tests conducted between the transconductance measurements. As discussed below, the present invention provides a method that allows for an accurate determination of the hot carrier lifetime within a very short period of time, (e.g., from about 0.001 seconds to about 100 seconds). This method, therefore, can be used to monitor the hot carrier lifetime quality of the devices as they are fabricated without substantial increases in production downtime typically required to make hot carrier lifetime measurements.
In one embodiment, the step of determining includes the step of determining the g
m1
as a function of a first source/drain current within a linear region of the transistor with respect to a first gate voltage. In another embodiment, the method may further include the step of applying the stress voltage to the transistor to cause further degradation of the transistor subsequent to the step of determining said g
m2
.
In yet another embodiment, the step of determining includes the step of determining the g
m2
as a function of a second source/drain current within a linear region of the transistor with respect to a second gate voltage.
In an advantageous embodiment, the stress voltage does not exceed about a maximum operating voltage of the transistor and a preferred stress voltage is a maximum operating voltage of the transistor. However, it should be understood that the stress voltage may also be about a normal operating voltage of the transistor.
In another advantageous embodiment, the transconducta
Chetlur Sundar
De Souza Merlyne M.
Oates Anthony S.
Brown Glenn W.
Lucent Technologies - Inc.
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