Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-09-25
2001-02-13
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S762010, C438S014000
Reexamination Certificate
active
06188233
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally directed to the testing of semiconductor devices, and, more particularly, to the testing of electrical characteristics of semiconductor devices.
2. Description of the Related Art
As the feature size of semiconductor devices continues to decrease, the effects of manufacturing a semiconductor device in proximity to other semiconductor devices, or other structures, e.g., metallic interconnect lines, becomes more pronounced. It is known that the actual feature size of a fabricated semiconductor device, for example, the gate width of a field effect transistor, may be different than the designed feature size of the device, i.e., a feature size of a semiconductor device as actually built may be different from the designed size of that feature. One factor that causes differences between the design feature size and the actual feature size is the proximity of the device under construction to other structures or other semiconductor devices. That is, features that are all designed to be the same size may measure one dimension when the semiconductor device is made in an isolated area, and may measure a different dimension when the same semiconductor device is fabricated in proximity to adjacent structures, e.g., other devices, interconnect lines, etc.
In integrated circuits, there are areas where the semiconductor devices, e.g., transistors, are densely packed, areas where the devices are isolated, and areas that fall somewhere between these two extremes. In general, densely packed regions of an integrated circuit are areas where the semiconductor devices are placed as close together as possible. Isolated devices are areas where there is little, if any, surrounding structure adjacent the semiconductor devices. There are also circuits in which the devices, e.g., transistors, are placed as close together as possible, yet still allow room for metal lines and contacts between the transistors, i.e., an intermediate density.
The change in the actual feature size of a semiconductor device, as compared to the designed feature size, can have many negative impacts on the electrical characteristics of the device. For example, in the case of field effect transistors, the variance in, for example, the channel length of the transistor due to manufacturing the transistor in proximity to other devices or structures can impact, among other things, the drive current consumed by the device during operations. Drive current tends to vary with the channel length of the device. In general, as the channel length decreases, the drive current and the leakage through the gate increases. The reduction in the channel length may also cause the circuit to use more power and potentially exceed the power supply specification for the particular circuit, i.e., it will consume more power than anticipated. That is, changes in feature sizes of semiconductor devices, e.g., changes in the channel length of transistors due to proximity effects, must be accounted for in designing integrated circuits.
Thus, it is desirable to develop a method for determining the impact on electrical characteristics of a semiconductor device due to changes in feature sizes as a result of fabricating the device in proximity to other structures. Such information may be useful in the design and manufacturing of integrated circuit devices. The present invention is directed to solving some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is directed to a method for determining the electrical characteristics of semiconductor devices due to the fabrication of the semiconductor devices in close proximity to other semiconductor devices or structures. The method comprises fabricating a plurality of semiconductor devices in a substrate, the plurality of devices being configured in an electrical series. The method further comprises biasing all but one of said semiconductor devices to an active state and, thereafter, biasing said one of said devices to an active state. The method also includes monitoring the electrical characteristics of said one of said semiconductor devices.
REFERENCES:
patent: 5477160 (1995-12-01), Love
patent: 5489851 (1996-02-01), Heumann et al.
patent: 5754410 (1998-05-01), Bardsley et al.
patent: 6026221 (2000-02-01), Ellison et al.
Michael Mark W.
Nistler John L.
Advanced Micro Devices , Inc.
Metjahic Safet
Tang Minh
Williams Morgan & Amerson P.C.
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