Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2001-04-11
2002-12-03
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C356S370000
Reexamination Certificate
active
06489173
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the field of electronic devices, and more particularly, to a method for inspecting the planarity of semiconductor circuit package leads.
BACKGROUND OF THE INVENTION
Integrated circuit packages have leads that connect external circuitry to the internal integrated circuits. The leads are formed generally of a metal conductor such as copper, or an iron alloy, and are cut and formed to a shape and dimension specified by the device type. If the integrated circuit device leaves the manufacturing process with any leads which are deformed and are unable to make good contact with the printed circuit board (PCB), an open or intermittent circuit often results.
A final inspection of the device is generally carried out at the manufacturing site prior to shipment in order to avoid costly failures, or additional inspection, with resulting work slow down at the user or PCB assembly site. In high volume semiconductor manufacturing sites, automated visual inspection systems, such as that illustrated in
FIG. 1
, are made by way of a computer based image processor
20
connected to a CCD camera
21
. A top view inspection system requires only a single camera
21
, and has the capability of inspecting devices
22
for parameters such as lead pitch, missing or extra leads, linearity, lead span, top side symbolization, and to some extent for lead planarity. Planarity failures occur when one or more leads are lifted either up or down so that the flat portion of the lead tip is unable to make contact with a seating plane below the device body. Top view inspection systems measure the distance a particular lead extends in comparison to a normal line of leads in a row, and to a set tolerance. More complex and expensive systems with multiple cameras are required if all aspects of lead planarity are to be inspected.
Adding more complexity to final lead inspection is the fact that many plastic packaged semiconductor devices are transported, stored, and assembled onto printed circuit boards from an embossed carrier tape, and the final inspection must be made after the device is situated in the carrier recess
23
. The carrier tape has become a predominant means of transport because it permits mounting of the electronic components to a PCB to be accomplished with increased efficiency, and facilitates handling of components, in particular semiconductor packages having fine pitch gull wing shaped leads.
In carrier tape format, each semiconductor device is positioned in a recess formed on a tape at predetermined intervals in a longitudinal direction, and the recess is covered by a thin film of tape which is adhered to the embossed carrier by an adhesive to close the opening. The final inspection carried out prior to shipment is made with the devices positioned in the carrier tape recess or pocket prior to cover tape positioning and sealing. However, it is not possible to make side-view inspection of devices in the recesses, and as a result some types of planarity failures are not detected by automated top-view inspection.
Planarity defects are significant because out of plane leads may result in continuity failures at printed circuit board (PCB) assembly. Fine pitch leads are typically composed of a highly ductile metal, such as copper and are readily deformed during handling processes. Final inspection of a device positioned in a carrier recess allows detection of errors recognizable from a top-view only. A planarity failure recognizable from the top view is a lead
25
which is lifted from its seating plane
26
, as illustrated in
FIGS. 2
a
and
2
b
. Clearly, the lead
25
is out of line from its neighboring leads
24
.
However, a planarity defect not recognized by top view inspection is one in which all leads in one row are lifted, or lowered uniformly from the seating plane
36
at the same angle, as illustrated in
FIGS. 3
a
and
3
b
. From an end view, as in
FIG. 3
a
, the defective leads
35
are readily distinguished from the correctly formed and seated leads
34
, but from a top view, as shown in
FIG. 3
b
, this defect is undetected because all the shiny metallic leads in a row appear to be uniform, and non-planarity is overlooked.
In particular, this defect will not be detected in devices situated in a tape or other carrier having a recessed pocket. Further, one cause of this defect has been traced to the device loading process itself, as illustrated in
FIG. 4
, wherein a leaded device
40
is slightly misplaced in a tape carrier pocket
41
, and the mechanical track cover
43
forces the device into its pocket, bending all leads
45
caught against the recess wall. In this example, the leads are all deformed upward, and at a uniform angle. Another mechanism leading to failures involving all leads at a uniform angle occurs when small semiconductor devices are forced into the receiving carrier by a jet of air, which may force a device positioned on its side to deform all leads on that row. Alternate carrier types include trays which have recesses in which the semiconductor devices are placed for shipment and mounting. As with carrier tapes, inspection is made from the top view, and may not detect some types of planarity failures.
It would be a significant advantage to the industry if a solution to this planarity defect analysis deficiency could be found, and in particular if the analysis would make use of existing lower cost top-view imaging systems, and if it were applicable to final inspection of devices within a carrier.
SUMMARY OF THE INVENTION
In accordance with the present invention, the problem of failure to detect non-planarity of multiple leads having the same offset angle from an integrated circuit package is resolved.
It is an object of the present invention to provide a sensitive, and accurate method for detecting lead planarity defects using top-view automated inspection equipment.
It is an object of the present invention to provide a method for analyzing lead planarity of semiconductor devices which have been placed in embossed carrier tape, or alternate recessed carrier format.
It is an object of the invention to provide a method for inspecting gull wing leaded devices.
It is further an object of the invention to provide a method for analysis of lead planarity which does not exist on current inspection systems.
It is an object of the invention to make use of existing vision inspection equipment.
It is an object of the invention to provide a method for analysis of lead planarity defects which avoids over compensation resulting in rejection of devices beyond the capability of manufacturing equipment.
The above objectives are realized by a new method for calculating lead planarity based on measured lead span, obtained from use of existing top-view visual inspection systems. The lead span of multiple leads on a predetermined number of good devices from a specific production lot are accurately measured, a mathematical model of the device defined, and the tolerances of the lot calculated. The lead span of each device under test in the production lot is then measured, and from the differences in lead span between the known good devices and the device under test, the planarity is calculated from a relationship between span and height above the seating plane, and any devices which are outside the defined tolerances are screened. Technical advantages of this recursive computational procedure assure capture of failed devices having a previously undetectable fault without exceeding the manufacturing capability, and specification for the particular device type.
In a preferred embodiment, thin small outline (TSSOP) plastic packages housed in an embossed carrier tape are characterized, and tolerances defined using the aforementioned method.
REFERENCES:
patent: 5309223 (1994-05-01), Konicek
Brady III W. James
Stevenson Andre′ C
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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