Method for determining instance placements in circuit layouts

Details Method for determining instance placements in circuit layouts Method for determining instance placements in circuit layouts

1994-12-12

1996-05-28

Trans, Vincent N.

Boots, shoes, and leggings

364490, G06F 1750

Patent

active

055218369

ABSTRACT:
A process for producing placement information for layouts of circuit elements of networks that are initially represented by netlists such that datapaths can be advantageously placed into a regular array. In one preferred embodiment, the method includes steps of encoding datapath information in instance names of a netlist generated by a datapath compiler; using the encoded datapath information for defining partitioned areas that preserve datapaths; and generating circuit layouts from the netlist, which layouts contain floor plans of the datapaths.

REFERENCES:
patent: 3617714 (1971-11-01), Kernighan
patent: 4922432 (1990-05-01), Kobayashi et al.
patent: 4967367 (1990-10-01), Piednoir
patent: 5187784 (1993-02-01), Dowson
"Partitioning and Placement Technique for CMOS Gate Arrays" by Odaware et al., IEEE Trans. on Computer-Aided Design, CAD-6, No. 3, 1987, pp. 355-362.
"A Class of Min-Cut Placement Algorithms" by Brener.
"A Procedure for Placement of Standard-Cell VLSi Circuits" by Dunlop et al., IEEE Trans. on Computer-Aided Design, CAD-4, No. 1, 1985, pp. 92-98.
Fiduccia, C. M. and Mattheyses, R. M.; "A Linear-Time Heuristic for Improving Network Partitions"; 19th Design Automation Conference; pp. 241-247.
F. K. Hwang, "The Rectilinear Steiner Problem", Design Automation Fault-Tolerant Computing, vol. 2, pp. 303-310, 1978 Computer Science Press, Inc.
M. R. Garey, D. S. Johnson and L. Sockmeyer, "Some simplified NP-complete graph problems", Theor. Computer Science, vol. 1, pp. 237-267.
M. A. Breuer, "Min-Cut Placement", Journal Design Automation Fault-Tolerant Computing, vol. 1, pp. 343-362, 1977.

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