Abrading – Precision device or process - or with condition responsive... – Computer controlled
Reexamination Certificate
2003-01-15
2004-06-01
Rachuba, M. (Department: 3723)
Abrading
Precision device or process - or with condition responsive...
Computer controlled
C451S041000, C451S054000, C438S011000, C438S018000, C438S691000, C438S692000
Reexamination Certificate
active
06743075
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
This application claims priority from R.O.C. Patent Application No. 091104999, filed Mar. 15, 2002, the entire disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a chemical mechanical polishing process for making chips and, more particularly, to a method for determining a chemical mechanical polishing time.
In recent years, in order to reduce operation costs and improve competitiveness, almost all integrated circuit (IC) companies have devoted to increasing the packing density of integrated circuits. To achieve this goal, the dimensions of elements have to be minimized, and the intervals between elements have also to be reduced. To meet this objective, it is preferable to have every layer of IC reaching global planarization. With the help from recent development of Chemical Mechanical Polishing (CMP) technology, the goal of global planarization becomes feasible. That is, the CMP technology has become a major key to making the increase of IC packing density possible.
Referring to
FIG. 1
, a cross-sectional view of a typical multi-layer IC is shown embedded. In this multi-layer IC, shallow trench isolations
12
for defining active devices are formed on a semiconductor substrate
10
through a conventional standard process. On the substrate
10
in addition to the shallow trench isolations
12
, metal oxide semiconductor field effect transistors (MOSFETs) are formed, in which the MOSFETs include gate dielectric layers
14
, gate conductive layers
16
, lightly doped sources/drains (not shown in the drawing), sources/drains
18
, silicon nitride sidewall spacers
20
, and silicon nitride caps
22
. The gate conductive layers
16
are formed by applying photolithography and ion etching on a first polysilicon layer. The nitride sidewall spacers
20
and the nitride caps
22
, with a total thickness of about 600 Å, are formed to serve as end points for a subsequent anisotropic etching process that develops self-aligned contacts. As shown, a first polysilicon inter-layer dielectric
23
is formed on the MOSFETs. A second polysilicon layer
24
developed from a polysilicon layer topping the first polysilicon inter-layer dielectric
23
is formed by applying also the photolithography and etching process. Another polysilicon layer for developing a third polysilicon layer
28
by the photolithography and etching process is provided onto a second polysilicon inter-layer dielectric
26
. Typically, a total thickness of the first polysilicon inter-layer dielectric
23
and the second polysilicon inter-layer dielectric
26
is about 3,500 Å. As shown in this typical layer structure, a top inter-layer dielectric
30
on the third polysilicon layer
28
is shown to be unexpectedly deposited with an undulating surface. In particular, the wafer comprising the undulating surface of the above IC structure can be planarized with a typical CMP process.
In reworking of the CMP process, for example, to polish an initial thickness of 20,000 Å of the inter-layer dielectric
30
to about 8000 Å, an endpoint detection technique is typically used to monitor the polishing to avoid over-polishing or under-polishing. The endpoint detection technique is performed by utilizing a laser beam to project onto the inter-layer dielectric
30
and then measuring a reflection intensity of the laser beam. The reflection intensity varies because of different interference effects resulting from different thicknesses of the remaining inter-layer dielectric
30
. By using the normal light intensity as the vertical coordinate and time as the horizontal coordinate, a gradient relationship between the light intensity and the time can be obtained to determine the remaining thickness of the dielectric
30
, and thereby the endpoint for the CMP process can be deduced. However, because of the complication of performing the aforesaid CMP technique and the non-linearity of the polishing, precision of thickness control cannot be guaranteed and thus the polishing quality usually suffers.
Still, there are other useful methods similar to the endpoint detection techniques. One approach is to form a pattern on the surface of a test wafer having the same thickness as the real wafer to be polished. The CMP process on the test wafer follows a trial-and-error manner that provides a shorter initial polishing time with gradually increasing polishing times thereafter. The initial shorter polishing time is preset to result in an insufficient polishing. Then, the polishing time is gradually increased until the polishing thickness meets certain preset requirements. The polishing time elapsed is then used as the endpoint time for the CMP process. However, such a method needs a lot of polishing tests and is both time-consuming and material-wasting. Furthermore, such a processing reduces the service life of the polishing machine. Yet, producing the pattern on the testing wafer surface takes a lot of time, and it is possible that the results inaccurately reflect the actual polishing conditions. Such an approach may also result in over-polishing or under-polishing.
Therefore, to develop a method for determining polishing time for CMP process is an important task in the IC industry.
BRIEF SUMMARY OF THE INVENTION
The present invention relates to a method for determining rapidly and accurately the polishing time of a chemical mechanical polishing process for polishing target wafers to avoid any problems of under-polishing or over-polishing. The method does so by polishing a control wafer to produce a progressive relationship of polishing thickness and respective polishing time thereof. Through an equivalent conversion approach, the method converts a polishing thickness of the target wafer into a corresponding or equivalent polishing thickness of the control wafer. Based on the progressive relationship for the control wafer, a polishing time for the target wafer is determined from the equivalent polishing thickness of the control wafer.
An aspect of the present invention is directed to a method for determining a chemical mechanical polishing time for removing a target polishing thickness H from an uneven surface of a target wafer. The method comprises polishing a control wafer by a chemical mechanical polishing to obtain a progressive relationship of polishing thickness and respective polishing time therefor. A first polishing time T1 is determined for removing a first thickness H1 from the target wafer, in which the first thickness H1 with substantially the uneven surface removed is smaller than the target polishing thickness H of the target wafer to be removed. In some embodiments, the first polishing time T1 is determined by polishing the target wafer to remove the first thickness H1 by chemical mechanical polishing. The method comprises calculating an image polishing thickness H1′ to be removed from the control wafer with respect to the first polishing time T1 according to the progressive relationship of the polishing thickness and respective polishing time for the control wafer. A second polishing thickness H2=(H−H1) is added to the image polishing thickness H1′ to obtain an equivalent polishing thickness H′ for the control wafer. A target polishing time is determined for removing the target polishing thickness H from the target wafer by interpolating the progressive relationship of the polishing thickness and respective polishing time for the control wafer based on the equivalent polishing thickness H′.
In some embodiments, the target wafer and the control wafer have the same polishing materials. In other embodiments, the target wafer and the control wafer have different polishing materials, and the method comprises converting a removal of the polishing material of the target wafer, through an equivalent conversion principle, to a corresponding removal of the polishing material of the control wafer in the same polishing time. The equivalent conversion principle converts a removal of
Lin Chun-Te
Liu Shan-An
Lu Ming-Hsien
Wu Chung-Ru
Mosel Vitelic Inc.
Rachuba M.
Townsend and Townsend / and Crew LLP
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