Method for determining an ESD/latch-up strength of an...

Details Method for determining an ESD/latch-up strength of an... Method for determining an ESD/latch-up strength of an...

2005-08-16

2005-08-16

Zarneke, David (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S765010, C324S1540PB, C324S762010, C361S111000

Reexamination Certificate

active

06930501

ABSTRACT:
A method for determining an ESD/latch-up strength of an integrated circuit includes producing an integrated circuit and a test structure using the same fabrication process. Electrical parameters at the test structure are measured and characteristic values associated with the integrated circuit are derived from the measured parameter values, wherein the characteristic values characterize an ESD or latch-up characteristic curve associated with the integrated circuit. The method further includes testing whether the characteristic values in each case lie within a predetermined range assigned to them, wherein the ranges are chosen such that a desired ESD/latch-up strength is present if the characteristic values in each case lie within their range.

REFERENCES:
patent: 5523252 (1996-06-01), Saito
patent: 5561373 (1996-10-01), Itoh
patent: 5654863 (1997-08-01), Davies
patent: 5675260 (1997-10-01), Consiglio
patent: 5818235 (1998-10-01), Simonov et al.
patent: 5923160 (1999-07-01), DeChiaro et al.
patent: 5978197 (1999-11-01), Chan
patent: 5990488 (1999-11-01), Nistler et al.
patent: 6205408 (2001-03-01), Jubin et al.
patent: 6265885 (2001-07-01), Luo et al.
patent: 05-256899 (1993-08-01), None
“Latch-Up Characterization Using Novel Test Structures and Instruments”, Carles Cané, Manuel Lozano, Enric Cabruja, José Anguita, Emilio Lora-Tamayo and Francisco Serra-Mestres, IEEE Transactions on Semiconductor Manufacturing, vol. 4, No. 3, Aug., 1991, pp. 199-205.
Modified Transmission Line Pulse System and Transistor Test Structures For The Study of ESD, Robert A. Ashton, Proceedings IEEE Int. Conference on Microelectronic Test Structures, vol. 8, Mar., 1995, pp. 127-132.

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