Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Including integrally formed optical element
Reexamination Certificate
2001-09-17
2003-02-04
Sherry, Michael (Department: 2829)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Including integrally formed optical element
Reexamination Certificate
active
06514783
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to electronic circuit packaging techniques. More particularly, the present invention relates to flip-chip interconnect techniques.
BACKGROUND OF THE INVENTION
Flip-chip mounting techniques are utilized to interconnect a chip-based electronic device to another device, a circuit board, a connecting substrate, or the like. Flip-chip devices typically include solder bumps that are bonded to contact pads located on the chip substrate. The solder bumps are reflowed to establish electrical and physical connections between the chip and the connected device, board, or substrate. Flip-chip techniques are gaining acceptance for use in high frequency applications having strict impedance matching requirements.
Flip-chip transition interfaces for high frequency applications typically are fed by coplanar waveguides or microstrip transmission lines that carry electronic signals. For example, the flip-chip device can include an output waveguide section and a transition or interconnect section for coupling the device to a second substrate. The second substrate can include a waveguide section and a corresponding transition or interconnect section for receiving the output signal generated by the device (this concept also applies where the first substrate receives an electrical signal from the second substrate). The two transition sections are connected together using solder bumps. Much of the prior art for millimeter wave and sub-millimeter wave electronic interface circuits has focused on the use of reactive matching networks to provide impedance matching at very high frequencies. Used in conjunction with circuit interconnects, reactive matching networks compensate for impedance mismatch between the characteristic impedance of the interconnect and the impedance of the source or load circuit. One aspect of using such compensating networks is that the impedance match is usually limited over a frequency range. In this regard, such matching circuits are common in high center frequency, fractional bandwidth systems.
Some prior art techniques attempt to provide a broadband impedance match to high frequencies, particularly in the digital optical communications sector, which requires both DC and high frequency components to reconstruct electronic information signals. High speed circuits that transmit and receive signals between other high speed circuits, and other optoelectronic devices, can achieve rise and fall times in the 10-13 picosecond range. Newer designs may require even lower rise and fall times, e.g., in the 6-8 picosecond range. The corresponding transition interface structures and interconnect circuits will need to accommodate bandwidths of up to 100 GHz to support these low rise and fall times.
Accordingly, a need exists for optimized flip-chip transition interface designs for high frequency and broad bandwidth applications.
BRIEF SUMMARY OF THE INVENTION
The techniques of the present invention may be employed to provide a flip-chip transition interface structure having acceptable broadband impedance matching characteristics. A transition interface structure according to the present invention employs a suitably designed ground cutout region surrounding the chip signal bond pad. In accordance with another aspect of the present invention, the layout of the transition interface structure contemplates the relative positioning of the solder bumps located on the output signal bond pad and on the surrounding ground elements.
The above and other aspects of the present invention may be carried out in one form by a flip-chip transition interface structure having a conductive signal element, a substantially round bond pad formed at an end of the conductive signal element, a first conductive reference element including a first substantially curved edge, a second conductive reference element including a second substantially curved edge, and a cutout region defined at least in part by the first curved edge and the second curved edge.
REFERENCES:
patent: 5528203 (1996-06-01), Mohwinkel et al.
patent: 5668512 (1997-09-01), Mohwinkel et al.
patent: 5717231 (1998-02-01), Tserng et al.
patent: 5719979 (1998-02-01), Furuyama
patent: 5767580 (1998-06-01), Rostoker
patent: 5987767 (1999-11-01), Huddleston et al.
patent: 6100775 (2000-08-01), Wen
patent: 6215377 (2001-04-01), Douriet
patent: 6365978 (2002-04-01), Ibnabdeljalil et al.
patent: 6369448 (2002-04-01), McCormick
Heinrich et al, “Millimeter-Wave Characteristics Of Flip-Chip Interconnects For Multichip Modules”, IEEE Transactions On Microwave Theory And Techniques, vol. 46, No. 12, Dec. 1998.
Hirose et al, “A Flip-Chip MMIC Design With Coplanar Waveguide Transmission Line In The W-Band”, IEEE Transactions On Microwave Theory And Techniques, vol. 46, No. 12, Dec. 1998.
Iwasaki et al, “Packaging Technology For 40-Gb/s Optical Receiver Module With An MU-Connector Interface”, IEEE 2000, Electronic Components And Technology Conference.
Applied Micro Circuits Corporation
Gray Cary Ware & Freidenrich
Meador Terrance A.
Sarkar Asok Kumar
Sherry Michael
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