Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
2002-03-26
2004-04-27
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S753000
Reexamination Certificate
active
06727189
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to detecting metal on a silicon chip, more particularly to detecting iron, aluminum, and manganese contamination on wafers.
In semiconductor manufacturing, deposition of undesired metal particles or ions, e.g., iron, aluminum, or manganese, may occur on the surface of wafers. This deposition contaminates the wafers. Because most wafer manufacturing tools are made of aluminum, aluminum contamination may be dominant and will diminish the quality of wafers. Conventionally, these metal particles or ions are detected by the element analyzer. However, there are detection limits for the element analyzer and the metal contamination may be hard to trace because the content is so low.
Conventionally, two instruments can be used to detect metal contamination on silicon chips. The first instrument is the Second Ion Mass Spectrometer (SIMS). In the procedure for using SIMS to detect metal contamination on silicon chips, the silicon chip is cut into the proper size for a test sample. Detection of contamination on the test sample is then conducted. The disadvantage of this method is that contamination detection is limited in the test sample, and it is therefore time-consuming to complete the examination on the whole silicon chip.
Another procedure uses the Total X-Ray Reflection Fluorescence analyzer (TXRF). The silicon chip is placed into the TXRF and is scanned by X-ray. The disadvantage is that the operation takes one hour and only detects what kind the metal contamination is but not its location.
BRIEF SUMMARY OF THE INVENTION
Embodiments of the present invention relate to implanting arsenic into a wafer to quickly detect if there is metal contamination, such as iron, aluminum, or manganese, on the wafer.
In one embodiment, the first step is to implant the arsenic ion into a silicon chip, where the arsenic ion will react with iron, aluminum, or manganese ions on the chip to form arsenide, e.g., iron arsenate, aluminum arsenate, or manganese arsenate. The implanting of arsenic ions to form arsenide with iron, aluminum, or manganese ions will create silicon defects on the silicon chip. The second step is to etch the silicon chip with acidic chemical etching solution. Because the etching rate on the silicon defects area is faster than on the uncontaminated area, after etching, the silicon defects will form silicon pits which are easily observed by means of optical or electron microscopy.
The advantage of the present invention is its short detection time, easy confirmation, and subsequent determination of the location of any metal contamination.
In accordance with an aspect of the present invention, a method for detecting metal contamination of a silicon chip comprises implanting arsenic ions into the silicon chip, and etching the silicon chip with a chemical etching solution. The existence of any metal contamination is detected by observing occurrence of silicon pits on the silicon chip caused by reaction between the arsenic ions and the metal contamination and etching with the chemical etching solution.
In some embodiments, the metal contamination comprises at least one of Fe, Al, and Mn. The chemical etching solution comprises an acid etching solution. The acid etching solution may comprise HF and HNO
3
. The acid etching solution may comprise at least one of (Cu(NO
3
)
2
.3H
2
O), CrO
3
, CH
3
COOH, HF, HNO
3
, and deionized water. The occurrence of silicon pits on the silicon chip is observed by microscopy.
In accordance with another aspect of the present invention, a method of detecting metal contamination on a silicon substrate comprises implanting arsenic ions into the silicon substrate, wherein the arsenic ions react with any metal contamination on the silicon substrate to form silicon defects. The silicon substrate is etched with a chemical etching solution to form silicon pits on locations of any silicon defects. The occurrence of any silicon pits on the locations is observed to detect metal contamination.
REFERENCES:
patent: 4508757 (1985-04-01), Fabricius et al.
patent: 4577396 (1986-03-01), Yamamoto et al.
patent: 5520769 (1996-05-01), Barrett et al.
patent: 5801416 (1998-09-01), Choi et al.
patent: 6528387 (2003-03-01), Moriyasu et al.
Chung Chi-Ping
Jou Chon-Shin
Lin Tsai-Sen
Wang Chuan-Yi
Chen Kin-Chan
Mosel Vitelic Inc.
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