Semiconductor device manufacturing: process – With measuring or testing – Optical characteristic sensed
Reexamination Certificate
2003-09-25
2004-10-19
Guerrero, Maria F. (Department: 2822)
Semiconductor device manufacturing: process
With measuring or testing
Optical characteristic sensed
C438S014000, C438S017000, C438S597000
Reexamination Certificate
active
06806104
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
This invention generally relates to a method of detecting semiconductor device, and more particularly to a method of detecting defect of a semiconductor device.
2. Description of the Related Art
An integrated circuit integrates devices and circuit into a 2 cm×2 cm or smaller area. Because it generally includes more than ten thousand solid-state devices, an integrated circuit is so called a microelectronic device. If a microelectronic device has a defect, the microelectronic device may not operate properly. Further, when the size of the device becomes smaller, it is very difficult to improve the yield rate. One of the key issues regarding the yield rate is the defect in the microelectronic device. Therefore, how to detect and reduce the defects is a very important issue in improving the yield rate.
The conventional method of detecting defects is to decap each layer of the device by etching and to analyze the defects in each layer. That is, the conventional method removes each layer from top to bottom and finds out the defects in each layer until the bottom layer of the device.
However, as the integration level of the device increases, the conventional method may not be applicable, especially for detecting the defects generated during the front-end process, because it takes a long time to decap each layer to find out if there is any defect in a particular layer. Further, the defect may be removed during the etching process so that the defect cannot be detected any more.
SUMMARY OF INVENTION
An object of the present invention is to provide a method of detecting defect of semiconductor device in order to precisely and quickly detect the defects in the device.
The present invention provides a method of detecting defect of semiconductor device. The semiconductor device at least includes a substrate, a gate, a source region, a drain region, a plug, an insulating layer and a conducting line. The plug electrically connects the source region or the drain region and is located above a portion of the gate. At least a defect exists between the plug and the gate. The method comprises: polishing the semiconductor device until the plug is not above the portion of the gate; cleaning the semiconductor device; removing the insulating layer between the gate and the plug; and detecting the defect between the plug and the gate.
In a preferred embodiment of the present invention, the polishing step further comprises polishing the semiconductor device to partially expose the gate. The cleaning step comprises using deionized water to clean the semiconductor device and drying the semiconductor device. The removing step comprises performing a wet etching process and performing a dry etching process.
The present invention polishes the semiconductor device until the plug above the gate is substantially removed and then the insulating layer between the gate and the plug is removed. Hence, the method of the present is capable of eliminating the defects occurring from removal steps using the wet etching processes and therefore the defect can be precisely and effectively detected.
The present invention provides a method of detecting defect of semiconductor device. The semiconductor device at least includes two adjacent conducting layers and an insulating layer. The insulating layer is disposed between the two adjacent conducting layers, wherein a defect exists between the two adjacent conducting layers. The method comprises: polishing the semiconductor device to partially expose the two adjacent conducting layers; removing the insulating layer between the two adjacent conducting layers; and detecting the defect between the two adjacent conducting layers.
In a preferred embodiment of the present invention, after the polishing step and before the removing step, the method further comprises cleaning the semiconductor device. The cleaning step comprises using deionized water to clean the semiconductor device and drying the semiconductor device. The removing step comprises a wet etching process or a dry etching process.
In a preferred embodiment of the present invention, the semiconductor device is polished until the two adjacent conducting layers are partially exposed and then the insulating layer between the two adjacent conducting layers is removed. Hence, the method of the present invention is capable of preventing the defect occurring due to removal steps using wet etching process, and therefore the defect can be precisely and effectively detected.
The above is a brief description of some deficiencies in the prior art and advantages of the present invention. Other features, advantages and embodiments of the invention will be apparent to those skilled in the art from the following description, accompanying drawings and appended claims.
REFERENCES:
patent: 6107201 (2000-08-01), Lee
patent: 6168960 (2001-01-01), Li
patent: 6258437 (2001-07-01), Jarvis
patent: 6593152 (2003-07-01), Nakasuji et al.
patent: 6709879 (2004-03-01), Yeh
patent: 2003/0124791 (2003-07-01), Summerfelt et al.
Chang Houng-Jie
Chang Sheng-Ju
Guerrero Maria F.
Jiang Chyun IP Office
Novacek Christy
Powerchip Semiconductor Corp.
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