Method for detecting clock failure and switching to backup clock

Details Method for detecting clock failure and switching to backup clock Method for detecting clock failure and switching to backup clock

1996-10-28

1998-10-27

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

Having selection between plural continuous waveforms

327 20, 327144, 327153, G01R 1900

Patent

active

058282432

ABSTRACT:
A clock failure detection circuit which monitors a clock by comparing the clock to at least one delayed version of itself is provided. The original clock and the delayed version will be offset, such that an edge of one of them can clock a logic circuit to determine if the clock is at the proper level. By setting up the delay so that a clock edge is generated when the clock signal should be low, for instance, a bad output signal will be provided whenever the clock is high instead. This could be caused by the clock being stuck high, or by an irregular pulse width.

REFERENCES:
patent: 5561390 (1996-10-01), Hiiragizawa
"Clock-fail circuit switches to alternate clock", Rick Downs, EDN Oct. 24, 1996.
"Low Skew CMOS PLL Clock Driver", Motorola Semiconductor Technical Data, MC88915, Motorola BR1333--Timing Solutions.

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