Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2007-10-02
2007-10-02
Rodriguez, Paul (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C714S811000, C716S030000
Reexamination Certificate
active
10172996
ABSTRACT:
A method for efficiently detecting bus contention from a register transfer level (RTL) description is provided. A bus contention occurs if more than two components try to propagate data onto a bus at the same time. The provided method simulates possible input combinations and detects whether there is a possibility for a bus contention. In addition, the provided method is designed for testability, therefore using the method, the designer may identify contention that may exist in test mode at the RTL level of the design even when such conditions may not occur in system mode. The method provides the designer with the input combination as well as the RTL statement that caused the contention. The method detects the bus contention by simulating a small number of input combinations.
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Atrenta Inc.
Guill Russ
Rodriguez Paul
Sughrue Mion Pllc.
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