Method for designing semiconductor integrated circuit and...

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system

Reexamination Certificate

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C703S014000, C703S015000, C716S030000

Reexamination Certificate

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06845349

ABSTRACT:
A program for automatically designing a logic circuit used for a method of designing a pass transistor circuit, by which the number of required transistors, delay time, power consumption and chip area of the pass transistor circuit is reduced. The program executes the following steps: a) receiving inputted logic functions which define the logical relationship between the inputs and the outputs, and an inputted target specification, b) generating a binary decision diagram from part of the logic functions received at (a), c) replacing the diagram nodes formed at (b) with pass transistor circuit, d) judging whether or not the simulation characteristics of the pass transistor circuit described in (c) meets the target specification described in (a), and executing the following steps when the judgment is “no”, e) replacing part of the diagram generated by the procedure described in (b) with another diagram, f) allocating a new binary decision diagram to the control inputs of the nodes of the replaced diagram prepared at (e), and g) repeating the steps (c) and (d) for the diagram prepared at (f).

REFERENCES:
patent: 4477904 (1984-10-01), Thorsrud
patent: 4541067 (1985-09-01), Whitaker
patent: 4912348 (1990-03-01), Maki et al.
patent: 5144582 (1992-09-01), Steele
patent: 5243538 (1993-09-01), Okuzawa et al.
patent: 5493504 (1996-02-01), Minato
patent: 5581202 (1996-12-01), Yano et al.
patent: 5649165 (1997-07-01), Jain et al.
patent: 6301692 (2001-10-01), Kumashiro et al.
patent: 1-216622 (1989-08-01), None
patent: 1-256219 (1989-10-01), None
patent: 4-112270 (1992-04-01), None
patent: 4-160589 (1992-06-01), None
patent: 6-20000 (1994-01-01), None
patent: 6-215065 (1994-08-01), None
patent: 7-168874 (1995-07-01), None
Berkelaar et al. “Efficient Orthonormality for Synthesis with Pass-Transistor Selectors”; IEEE ICCAD-95 ; pp. 256-263; Nov. 1995.*
Information Processing Society of Japan, Journal of Information Processing, vol. 34, No. 5, May 1993, pp. 593-599.
Information Processing Society of Japan, Proceedings of 1994 Autumn National Conference, vol. A, p. 64.
Proceedings of IEEE 1994 Custom Integrated Circuits Conference, 1994, pp. 603-606.
IEEE Transactions on Computers, vol. C-35, No. 8, Aug. 1986, pp. 577-691.
Proceedings of the Information Processing Society 44th National Congress, pp. 6-143 to 6-144, no date.
IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2, Apr. 1987, “CMOS Differential Pass-Transistor Logic Design”, Pasternak et al, pp. 216-222.
IEEE Journal of Solid-State Circuits, vol. SC-25, No. 2, Apr. 1990, “A 3.8-ns CMOS 16×16-b Multiplier Using Complementary Pass-Transistor Logic”, Yano et al, pp. 388-395.
IEEE 1994 Custom Integrated Circuits Conference, 1994 Digest, “Lean Integration: Achieving a Quantum Leap in Performance and Cost of Logic LSIs”, Yano et al, pp. 603-606.
Proceeding of the 1994 Autumn Convention of the Institute of Electronics, Information and Communication Engineers of Japan, Edition of Fundamentals and Interfaces, p. 64.
IEEE Transactions on Computers, vol. C-35, No. 9, Aug. 1986, “Graph-Based Algorithms for Boolean Function Manipulation”, R. Bryant, pp. 677-691.
Digest of Technical Papers of IEEE 1995 Symposium on Low Power Electronics, 1995, “Multi-Level Pass-Transistor Logic for Low-Power ULSIs”, Y. Sasaki et al, pp. 14-15.
Tai: Pipelined Fault Simulation on Parallel Machines using the circuit flow graph; 1993 IEEE Int. Cont. on Comp. Design; pp. 564-567 10/93.
Caban et al.; A parallel BDD engine for logic verification; 5th annual IEEE Int. ASIC Conf., pp. 499-502 9/92.
Fujita et al.; Automatic and semi-automatic verification of switch-level circuits with temporal logic and binary decision diagrams; ICCAD-90; pp. 38-41 11/90.

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