Boots – shoes – and leggings
Patent
1996-10-15
1999-07-13
Teska, Kevin J.
Boots, shoes, and leggings
364488, G06F 1750
Patent
active
059235691
ABSTRACT:
First of all, a given logic circuit is divided into a combinational circuit portion and a register portion. The combinational circuit portion obtained by division is divided into a plurality of partial circuits having high connectivity. Each partial circuit is converted into a circuit having the transistor level. Then, a layout cell of the partial circuit having the transistor level is generated. Thereafter, arrangement and wiring are performed by using, as unit cells, a layout cell which corresponds to each register included in the register portion and the layout cell for each partial circuit in the combinational circuit so that a block layout is created. Accordingly, a layout having excellent characteristics can be created by a few kinds of cells in both circuits having the CMOS logic and the pass-transistor logic. In particular, the partial circuits having high connectivity are arranged in a cell in the circuit using the pass-transistor logic. Consequently, the optimum driving capability can be obtained and the layout having stable characteristics can be created. In addition, it is possible to ensure the superiority such as a reduction in area, the low consumed power, high-speed operation and the like.
REFERENCES:
patent: 5341309 (1994-08-01), Kawata
patent: 5473547 (1995-12-01), Muroga
patent: 5493506 (1996-02-01), Sakashita et al.
patent: 5517132 (1996-05-01), Ohara
patent: 5519627 (1996-05-01), Mahmood et al.
patent: 5530843 (1996-06-01), Koyama
patent: 5537580 (1996-07-01), Giomi et al.
patent: 5544066 (1996-08-01), Rostoker et al.
patent: 5633807 (1997-05-01), Fishburn et al.
patent: 5666288 (1997-09-01), Jones et al.
patent: 5734572 (1998-03-01), Guignet
IEEE Journal of Solid State Circuits "A 3.8-ns CMOS 16.times.16-b Multiplier Using Complementary Pass-Transistor Logic", K. Yano, T Yamanaka, T. Nishida, M. Saito, K. Simohigashi and A. Shimizu. pp. 388-395, vol. 25, No. 2, Apr. 1990.
IEEE 1994 Custom Integrated Circuits Conference "A High Speed Low Power, Swing Restored Pass-Transsistor logic Based Mulitply And Accumulate Circuit For Multimedia Applications" A. Parameswar, H. Hara, T. Sakurai, pp. 278-281.
IEEE 1994 Custom Integrated Circuits Conference "Lean Integration: Achieving A Quantum Leap In Preformance And Cost Of Logic LSIs" K. Yano, Y. Sasaki, K. Rikino, and K. Seki, pp. 603-606.
1995 Symposium on VLSI Circuits Degist of Technical Parers "Pass Trasnsistor Based Gate Array Architecture", Y. Sasaki, K. Yano, M. Hiraki, K. Rikino, M. Miyamoto, T. Matsuura, T. Nishida, and K. Seki, pp. 123-124.
Kumashiro Shinichi
Mae Youichirou
Mizuno Hiroshi
Moriwaki Toshiyuki
Tanaka Yasuhiro
Garbowski Leigh Marie
Matsushita Electric - Industrial Co., Ltd.
Teska Kevin J.
LandOfFree
Method for designing layout of semiconductor integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for designing layout of semiconductor integrated circuit , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for designing layout of semiconductor integrated circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2282624