Method for designing layout of semiconductor integrated circuit,

Details Method for designing layout of semiconductor integrated circuit, Method for designing layout of semiconductor integrated circuit,

1998-09-15

1999-11-09

Teska, Kevin J.

3955004, G06F 1750

Patent

active

059830085

ABSTRACT:
First of all, a given logic circuit is divided into a combinational circuit portion and a register portion. The combinational circuit portion obtained by division is divided into a plurality of partial circuits having high connectivity. Each partial circuit is converted into a circuit having the transistor level. Then, a layout cell of the partial circuit having the transistor level is generated. Thereafter, arrangement and wiring are performed by using, as unit cells, a layout cell which corresponds to each register included in the register portion and the layout cell for each partial circuit in the combinational circuit so that a block layout is created. Accordingly, a layout having excellent characteristics can be created by a few kinds of cells in both circuits having the CMOS logic and the pass-transistor logic. In particular, the partial circuits having high connectivity are arranged in a cell in the circuit using the pass-transistor logic. Consequently, the optimum driving capability can be obtained and the layout having stable characteristics can be created. In addition, it is possible to ensure the superiority such as a reduction in area, the low consumed power, high-speed operation and the like.

REFERENCES:
patent: 4924430 (1990-05-01), Zasio et al.
patent: 5095454 (1992-03-01), Huang
patent: 5400270 (1995-03-01), Fukui et al.
patent: 5555187 (1996-09-01), Spyrou
patent: 5706205 (1998-01-01), Masuda et al.
patent: 5726902 (1998-03-01), Mahmood et al.
patent: 5790830 (1998-08-01), Segal
patent: 5831869 (1998-11-01), Ellis et al.
patent: 5872716 (1999-02-01), Yano et al.

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