Data processing: structural design – modeling – simulation – and em – Modeling by mathematical expression
Patent
1999-06-23
2000-10-10
Stamber, Eric W.
Data processing: structural design, modeling, simulation, and em
Modeling by mathematical expression
716 5, G06F 1710
Patent
active
061310786
ABSTRACT:
A computer implemented method for verifying that a circuit or other system satisfies its specifications, is based on creating a first Boolean formula G representative of the system and its specification and through a series of steps creating a second formula G' having a known logical relationship to G and using the second formula G' to determine whether the system satisfies its specification.
REFERENCES:
patent: 5243538 (1993-09-01), Okuzawa
patent: 5359537 (1994-10-01), Saucier
patent: 5465216 (1995-11-01), Rotem
patent: 5504690 (1996-04-01), Kageyama
patent: 5649165 (1997-07-01), Jain et al.
patent: 6026222 (2000-02-01), Gupta et al.
G.D. Hachtel et al., "Verification Algorithms for VLSI Synthesis", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, No. 5, May 1988, pp. 616-640.
P. Lammens et al., "Correctness Verification of VLSI Modules Supported by a Very Efficient Poolean Prover", 1989 Int'l Conf. On Computer Design: VLSI in Computers and Processors, ICCD '89, pp.266-269.
E. Cerny, "A Compositional Transformation for Formal Verification", 1991 IEEE Int'l Conf. On Computer Design: VLSI in Computers and Processors, ICCD '91, pp. 240-244.
P. Jain et al., "Hierarchical Constraint Solving in the Parametric Form with Applications to Efficient Symbolic Simulation Based Verification", 1993 Int'l Conf. On Computer Design: VLSI in Computers and Processors, ICCD '93, pp. 304-307.
M. Agrawal et al., "The Boolean Isomorphism Problem", 37th Annual Symposium on Foundations of Computer Science, 1996, pp. 422-430.
Allen Van Gelder, "A Propositional Theorem Prover to Solve Planning and Other Problems,"Annals of Mathematics & Artifical Intelligence, (Aug. 9, 1998).
Tracy Larrabee,"Test Pattern Generation Using Boolean Satisfiability," Transactions on Computer Aided Design, vol. II (No. 1), (Aug. 9, 1992).
Hantao Zhang, "SATO: An Efficient Propositional Prover," International Conference on Automated Deduction--printed in LNAI #1249, Springer-Verlag, p. 272-275, (Aug. 9, 1997).
Randal Bryant, "Graph-Based Algorithms for Boolean Function Manipulations," IEEE Transactions on Computers 35:8, p. 677-691, (Aug. 9, 1986).
Randal Bryant, "Symbolic Boolean Manipulation With Ordered Binary Decision Diagrams," ACM Computing Surveys, (Aug. 9, 1992).
Biere et al., "Symbolic Model Checking Without BBD's," TACA '99 Lecture Notes in Computer Science, Springer-Verlag, (Aug. 9, 1999).
M. Davis; H. Putnam, "A Computing Procedure for Quantative Theory," Journal of Association for Computing Machinery, vol. 7 (No. 3), (Aug. 9, 1960).
Frejd Russell W.
Stamber Eric W.
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