Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
1999-10-28
2001-06-12
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S462000, C438S800000
Reexamination Certificate
active
06245634
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to apparatus and techniques for the design and manufacture of semiconductor devices generally.
BACKGROUND OF THE INVENTION
Semiconductor devices, such as ASICs, have traditionally been manufactured by ASIC design and fabrication houses having both ASIC design and fabrication capabilities. Recently, however, the design and fabrication functionalities have become bifurcated, such that a customer may bring his fabready design to a fabrication house, having no design capability. The customer may employ conventionally available cell libraries, such as those available, for example, from Artisan or Mentor Graphics together with known design rules, to design their own devices.
Semiconductor design modules having specific functions, known as cores, are also available for integration by a customer into his design. An example of a commercially available core is a CPU core, commercially available from ARM Ltd. of Cambridge, England.
Cores may be provided in a variety of forms. For example, a “soft core” may be in the form of a high level schematic, termed RTL, while a “hard core” may be at a layout level and be designed to specific fabrication design rules.
SUMMARY OF THE INVENTION
The present invention seeks to provide a method for automatic distribution and licensing of semiconductor device cores, particularly “hard cores” as well as a modifiable core particularly suitable for use in the method.
There is thus provided in accordance with a preferred embodiment of the present invention a method for design and manufacture of semiconductors including producing a fab-ready design for a semiconductor device by importing into the design at least one core from a remote source, the core bearing an identification indicium, utilizing the fab-ready design to fabricate the semiconductor device and reading the identification indicium from the semiconductor device to indicate incorporation of the at least one core therein.
In accordance with a preferred embodiment of the present invention, there is provided a programmable or customizable core structure which can be incorporated in a design for a semiconductor device and which enables a user to assemble therewithin both conventional cores and programmable and customizable elements associatable therewith.
In accordance with a preferred embodiment of the present invention, the importing step includes communication of the core via a communications link, preferably the Internet.
Preferably, the reading step is associated with a reporting step which preferably includes reporting to an entity identified in the indicium the quantities and/or sizes of cores fabricated. This reporting step is preferably carried out by the fabrication facilities, preferably the foundry or mask shop as defined hereinbelow.
As the price of tooling and manufacturing such S.O.C's is rapidly growing, and may be expected to exceed the $1 m mark for a 0.12 micron process, it is desirable to share and spread the costs of tooling amongst several customers.
Thus, in accordance with yet another preferred embodiment of the present invention, the method for designing and manufacturing semiconductors may also include the use of a company or body which provides the various services and resources required by a customer to design a required system on a chip (S.O.C.).
In the present specification and claims, the company which provides this service is known as a “Virtual ASIC” company.
An effective way for organizing this service is for the Virtual ASIC company to collate many different S.O.C. designs, which have been developed by other companies and include a wide range of previously built-in options. Each entry into the library or data bank, includes the S.O.C. identification in addition to the identification of the individual core included in it. The Virtual ASIC company would then store all the information in a data bank or library and make it available to different customers.
A customer wishing to design an S.O.C., chooses a device, from the data bank, which is similar to his design requirements. The customer finalizes his own S.O.C. design based on the device design and data stored in the library. A completed S.O.C. design bears the S.O.C. identification, in addition to the identification of the individual core included in it. On completing the design of the S.O.C., the customer may update the data bank held by the Virtual ASIC company with his S.O.C. design and data.
As described by the previous embodiments of the present invention, these design S.O.C.'s may include dedicated computerized functions, such as processors, DSP, and programmable and/or customizable logic.
Using different methods, such as known in the art computer codes, the Virtual ASIC company may calculate the costs for NRE and production which may result from the wafer costs, the royalty obligations to the various bodies which provided the cores, and to the S.O.C. integrator and the other service and customization charges.
Thus, the customer is now able to review the technical capabilities of the chip, the required NRE and the production costs of his design. If the all the requirements of the customer are fulfilled, the customer now go ahead and order the chip.
It is appreciated that such a service may be provided over the Internet to a customer who is interested to implement his own application based on the similar S.O.C. devices which are stored in the data bank of the Virtual ASIC.
The customer may include his own software code for the processors and/or the DSP and to program and/or customize the logic to meet the customer's own particular needs and requirements.
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“Sun offers open-source Sparc to ignite SoC designs” EE Times, Aug. 1999; http://www.eet.com/story/OEG1999909140016. Dated Printed Copy.
Details about design support and IP cores from t
Bowers Charles
eASIC Corporation
Gluck Jeffrey W.
Thompson Craig
Venable
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